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W-lvetica#|x`H1`D4PkC"S^11>bbu"::Dg1:11bbbbbbbbbb11gggbuuuk1Xubuukuuuk111Rb:bbXbb1bb''X'bbbb:X1bXXXX;.;g:=::m:::mmmmm::::::mm:k1mubububububXubububub11111111bbbbbbbbbuXubbkbuXmmmmumububXXXXbububububbmbbbbbb:k:k::=kmmX:uXb'b:b:b:b'bmbbbb:::uXuXuXuXk:k:k:mbbbmbuXkXkXKQmmmm^b:kbbbbmbA@mmbmmbmmmmmmm:b:mmmbbmmmmmmmmmmmmXXmmmmmmmmmmmmmmmmmmcm`m`mm`m:mmmmmm}}}mjjmmmmmmmmmmmmmmm0mm}mmmmmmmmmmmmmmmmmmmmmmm}Mmmmmmmmmmmmmjmmmtmmmmmmmmm`'mmm`mmjmlWmmmmmmmmmmmmmmmmmmmW`mmmmjmMQMS PS Jet Plus /800 II QPJPII.PRSPl`D4PkCg2W_qD|xHelveticaCourier@,`H1`D4PkCmQrrr r  @C2 KLTG@,`H1`D4PkCmQrrr r  @C;,>>> >  @C ` X` hp x (#%'H   x|@  3'3'Standard6'6'StandardC6QMS $=R- Ot2  ` `  <  <AP IX142E OOt  ` `  <  <AP IX142E O:cm (3291) : (3291)    7.HRecommendation G.709 <SYNCHRONOUS MULTIPLEXING STRUCTURE HThe CCITT, considering  `  Hthat RecommendationG.707 describes the advantages offered by a synchronous digital hierarchy and multiplexing method and specifies a set of synchronous digital hierarchy bit rates; Hthat RecommendationG.708 specifies  8 H   the general principles and frame structure of the Network Node Interface (NNI) for the synchronous digital hierarchy;Ơ# H   the overall frame size of 9 rows x 270 columns and Section Overhead (SOH) definition and its byte allocation;Ơ# H   arrangements for international synchronous interconnection of STM1s;Ơ# Hthat RecommendationsG.707, G.708 and G.709 form a coherent set of specifications for the synchronous digital hierarchy and NNI; recommends Hthat the formats for mapping multiplexing elements into the STM1 at the Network Node Interface (NNI) and the method of multiplexing to STMN shall be as described in this Recommendation. 1.HBasic multiplexing structure HDescriptions of the various multiplexing elements are given in Recommendation G.708. HThe relationships between the various multiplexing elements are shown in Figure 1.1/G.709. The detailed multiplexing structure is described in the following sections. 2.HMapping formats and multiplexing method 2.1HMapping and multiplexing up to STM1 2.1.1HMapping of VC4 into AU4  8 HThe STM1 mapping format for transporting one VC4 in an AU4 is shown in Figure 2.1/G.709. The VC4 consists of a 9row by 261column payload structure; the first column of the VC4 is devoted to Path Overhead (POH). The payload of the VC4 shown in Figure 2.1/G.709 is a single C4. Other possible VC4 payloads include a single 139 264 kbit/s signal in a C4, four VC31s (shown in Figure 2.2/G.709 and carried in four TU31s), three VC32s (shown in Figure 2.3/G.709 and carried in three TU32s), and a group of either 21 TUG21s or 16 TUG22s (shown in Figure 2.4/G.709). HThe STM1 format shown in Figure 2.1/G.709 consists of an AU4 plus Section Overhead (SOH). The VC4 does not have a fixed phase with respect to the AU4 (and N* the STM1); therefore, the location of the first byte of the VC4 with respect to the AU4 frame is given by the AU4 pointer. Note that the AU4, including the AU4 pointer, has a fixed location in the STM1 frame. 2.1.2HMapping of four VC31s into AU4 HThe STM1 mapping format for transporting four VC31s in an AU4 is shown in Figure2.2/G.709. Each TU31 consists of a 9row by 64column payload structure plus six bytes of POH plus a three byte TU31 pointer. The payload of the VC31 shown in Figure2.2/G.709 is a single C31. Other possible VC31 payloads include a single 34 368 kbit/s signal in a C31 (shown in Figure5.10/G.709) or a group of either five TUG21s or four TUG22s (shown in Figure 2.5/G.709). HThe four VC31s are carried independently in the 261column VC4. Each of the VC31s does not have a fixed phase with respect to the start of the VC4. Therefore, the location of the first byte of each VC31 with respect to the VC4 POH is given by a 3byte TU32 pointer (H1, H2, H3). These four pointers reside in a fixed location in the VC4 as shown in Figure 2.2/G.709. HAs described in section 2.1.1, the phase of the VC4 with respect to the AU4 is given by the AU4 pointer. 2.1.3HMapping of three VC32s into AU4 HThe STM1 mapping format for transporting three VC32s in an AU4 is shown in Figure 2.3/G.709. Each TU32 consists of a 9row by 84column payload structure plus one column of POH and one 3byte TU32 pointer. The payload of the VC32 shown in Figure 2.3/G.709 is a single C32. Other possible VC32 payloads include a single 44 736 kbit/s signal in a C32 at a group of seven TUG21s (shown in Figure 2.5/G.709). HThe three VC32s are carried independently in the 261column VC4. Each of the VC32s does not have a fixed phase with respect to the start of the VC4.  h Therefore, the location of the first byte of each VC32 with respect to the VC4 POH is given by a 3byte TU32 pointer (H1, H2, H3). These three TU32 pointers reside in a fixed location in the VC4 as shown in Figure 2.3/G.709; 36 fixed stuff bytes are also required in the VC4. HAs described in section 2.1.1, the phase of the VC4 with respect to the AU4 is given by the AU4 pointer. 2.1.4HMapping of TUG2s into AU4 HThe STM1 mapping format transporting TUG21s and TUG22s in an AU4 is shown in Figure 2.4/G.709. The AU4 can carry a group of either 21 TUG21s or 16 TUG22s. HThe TUG21 payload structure has 9 rows and 12 columns. When used to transport TUG21s, the VC4 consists of one column of VC4 POH, eight columns of fixed stuff, and a remaining 252column payload structure. The 21 TUG21s are mapped into this 9row by 252column structure using a fixed phase with respect to the VC4. The TUG21s are single byte interleaved at a time as shown in Figure 2.4/G.709. HThe TUG22 payload structure has 9 rows and 16 columns. The VC4 consists of one column of CV4 POH, four columns of fixed stuff and 256 payload columns when used to carry the 16 TUG22s. The TUG22s are single byte interleaved into the 9row by 256column structure.  N*ԌHAs described in section 2.1.1, the phase of the VC4 with respect to the AU4 is given by the AU4 pointer. 2.1.5HMapping of four AU31s into STM1 HThe STM1 mapping format for transporting four VC31s within four AU31s is shown in Figure 2.6/G.709. A VC31 is defined to be a 9row by 64column payload structure, plus six bytes of POH, located in row 1 to 6 of the first column, according to the figure. HEach AU31 has a fixed phase with respect to the STM1 frame. As shown in Figure 2.6/G.709, the four AU31 pointers are located in column 11 to 14, row1 to 3 of the STM1, one pointer in each column. Column 11 to 270 of the STM1 are divided between each of the AU31s; thus, each AU31 occupies alternately every fourth column. HThe phase of each VC31 is not fixed with respect to its AU31. Therefore, the location of the first byte of each VC31 with respect to the AU31 frame is given by AU31 pointer (H1, H2,H3). The payload of the VC31 shown in Figure 2.6/G.709 is a single C31. Other possible VC31 payloads include a single 34 368 kbit/s signal in a C31 and a group of five TUG21s or four TUG22s (shown in Figure 2.5/G.709). 2.1.6HMapping of three AU32s into STM1 HThe STM1 mapping format for transporting three CV32s within three AU32s is shown in Figure 2.7/G.709. A VC32 is defined to be a 9row by 85column payload structure, with the first column consisting of VC32 POH. When mapped into its AU32, two columns of fixed stuff are added to each VC32 payload to make it equal the AU32 payload capacity. These two fixed stuff columns are fixed with respect to the VC32 POH and are inserted between columns 29 and 30, and between columns 57 and 58 of the VC32. HEach AU32 has a fixed phase with respect to the STM1 frame. As shown in Figure 2.7/G.709, the three AU32 pointers are located in the fourth row of the first nine columns of the STM1 frame, between the bytes of the SOH. The remaining 261 columns of the STM1 are divided between each of the AU32s; thus, each AU32 occupies alternately every third column of the 261. AU32 number one consists of three bytes of AU32 pointer, plus STM1 columns 10, 13, 16,... where columns 1 through 9 contain the SOH and the AU32 pointers. HThe phase of each VC32 (plus fixed stuff columns) is not fixed with respect to its AU32. Therefore, the locations of the first byte of each VC32 with respect to the AU32 frame is given by the AU32 pointer (H1, H2, H3). The payload of the VC32 shown in Figure 2.7/G.709 is a single C32. Other possible VC32 payloads include a single 44 736 kbit/s signal into a C32 (shown in Figure 5.8/G.709) and a group of seven TUG21s (shown in Figure 2.5/G.709). 2.1.7HMapping of TUGs into a VC HFigure 2.5/G.709 shows the schematic mapping of TUG2s into a VC3. The details of these mappings are given in section 5; this section presents the general multiplexing principles involved. HThe VC31 consists of six bytes of VC31 POH plus a 9row by 64column payload structure. This payload structure can be used to carry five TUG21s or four TUG22s. The individual TUG2 has a fixed location in the VC31 frame; this is shown schematically in Figure 2.5/G.709.  N*ԌHThe VC32 consists of nine bytes of VC32 POH plus a 9row by 84column payload structure. This payload structure can be used to carry seven TUG21s. Again, the individual TUG21 has a fixed location in the VC32 frame. HEach TUG21 can carry a single VC21 or four VC11s or three VC12s. Each TUG22 can carry a single VC22 or four VC12s or five VC11s. The VCs do not have a fixed phase with respect to the VC3 POH; TU pointers are used to indicate the position of the VCs in the TUG frame. 2.2HSTMN multiplexing 2.2.1HSTMN frame format HThe STMN signal is formed by single byte interleaving N STM1 signals. The STMN frame structure is depicted in Figure 2.8/G.709. HThe first byte of the STMN signal shall be the first A1 framing byte from STM1 #1 followed sequentially by the first A1 byte from STM1 #2 through #N. The first bit to be transmitted shall be the most significant bit of the first A1 framing byte from STM1 #1. HBefore byte interleaving STM1 signals to form a STMN signal, all of the SOH and the AUn (n = 3 or 4) pointers in the signals to be interleaved must be 125 s frame aligned. The alignment is accomplished by adjusting the values of the AUn pointers to reflect the new relative positions of the VCns. HNote that is is permitted to mix STM1s containing AU3s and STM1s containing AU4s in the same STMN. 2.2.2HSTMN interleaving HIf an STMN level signal is input to a byte interleaver with STMM level output (M > N), N bytes of each STMN are consecutively placed on the output STMM signal. This method of interleaving is illustrated in Figure2.9/G.709 where STMX, STMY and STMZ (X + Y + Z = M) inputs are sequentially interleaved to form an STMM output. 2.2.3HConcatenated STM1s HSTM1 signals can be concatenated together to form a STMNc which can transport payloads requiring greater than one C4 capacity. A concatenation indication, used to show that this multi C4 payload carried in a single VC4Nc should be kept together, is contained in the AU4 pointer. See section 3.4 for details. 2.3HMaintenance signals 2.3.1HSection maintenance signals HThe section AIS is detected as an all "1"s in bits 6, 7, 8 of byte K2 after descrambling. HFar End Receive Failure (FERF) is to return an indication to the transmitting STMN MUX that the receiving STMN MUX has detected an incoming section failure or is receiving section AIS. HFERF is detected by a "110" code in bit positions 6, 7 and 8 of the K2APS byte after descrambling. N*Ԍ 2.3.2HPath maintenance signals HThe VCn (n = 3, 4) unequipped indication is all "0"s VCn path signal label after descrambling. This code indicates to VCn terminating equipment that the VCn is intentionally unoccupied so that alarms can be inhibited. This code is generated as an all "O"s VCn path signal label and a valid VCn path BIP8(B3); the VCn payload is unspecified. HAn Alarm Indication Signal (AIS) is a signal sent downstream as an indication that an upstream failure has been detected and alarmed. The TUn (n=1, 2, 3) path AIS is specified as all "1"s in the entire TUn, including the TUn pointer. Similarly, the AUn (n = 3, 4) path AIS is specified as all "1"s in the entire AUn, including the AUn pointer. All path AIS's are carried within STMN signals having valid SOH. HThe path status byte (G1) is used to convey to the originator of a VCn (n = 3 or 4) the terminating path status and performance. Bits 1 through 4 convey the count of errors detected using the path BIP8 code. This code has nine legal values, 08. The remaining seven possible values should be interpreted as zero errors. 2.4HTiming recovery HThe STMN (N  1) signal must have sufficient bit timing content at the NNI. A suitable bit pattern, which prevents a long sequence of "1"s and "0"s, is provided by using a scrambler. Its operation shall be functionally identical to that of a frame synchronous scrambler of sequence length 127 operating at the line rate. HThe generating polynomial shall be 1 + X6 + X7. Figure2.10/G.709 gives a functional diagram of the frame synchronous scrambler. HThe scrambler shall be reset to "1111111" on the most significant bit of the byte following the last byte of the first row of the STMN SOH. (This is the most significant bit of the 9 x N + 1 transmitted byte of the STMN; see Figure2.8/G.709.) This bit, and all subsequent bits to be scrambled shall be added modulo 2 to the output from the X7 position of the scrambler. The scrambler shall run continuously throughout the complete STMN frame. HThe first row of the STMN SOH (9 x N bytes, including the A1 and A2 framing bytes) shall not be scrambled. Note Care should be taken in selecting the binary content of the bytes reserved for national use and which are excluded from the scrambling process of the STMN signal to ensure that long sequences of "1"s or "0"s do not occur. 2.5HConceptual steps for STMN assembly HFor a better understanding of the detailed structure of the STMN frame shown in Figure 2.8/G.709, the conceptual steps required to assemble the STMN frames in the direct (non nested) arrangement are listed: HHX HH1)  Each VCn (n = 3 or 4) has either six or nine bytes devoted to Past Overhead (POH) functions. Of these, the BIP8 error check byte (B3) is calculated over the entire contents of the VCn and the result is placed in the B3 byte of the following frame.p& H If it is appropriate, the VCn unequipped signal consisting of an all "0"s pattern for the VCn is inserted. (See section 2.3.)p& N*Ԍ HHX HH2)  After all of the required VCns have been assembled, AUn pointer values are calculated so as to frame align all of the AUns within a single STMN frame.p& H If the contents of the VCn are lost due to an equipment or other failure, the AUn path AIS signal is inserted into the AUn. The AUn path is defined in section 2.3.p& HHX HH3)  The SOH bytes are then added to the STMN frame. It is convenient to consider the last five rows of the SOH first. Of the N x 45 such SOH bytes, N x 9 are allocated to the N x 3 B2, N x 3 Z1 and N x 3 Z2 bytes. Thus, each STM1 has a full complement (3) of these bytes in the STMN. The remaining STMN SOH bytes in the last five rows (K1 and K2, D4 D12 and E2) are limited to the first STM1 in any STMN signal. The content of the unused SOH bytes of STM1 #2 through #N are for national use.p& HHX HH4)  The N x 3 B2 bytes of a STMN contain a bit interleaved parity Nx24 (BIPN x 24) code using even parity which is calculated across the entire previous STMN frame excluding the first three rows of SOH.p& HHX HH5)  A line signal failure would result in the insertion of a sectionAIS at this point in the assembly of an STMN (see section 2.3).p& HHX HH6)  The remaining bytes of SOH contained in the first three rows (27xN bytes) of the STMN are added next. Of these, the B1, E1, F1, D1D3 bytes are present only in STM1 #1 of any STMN signal. The context of the unused SOH bytes of STM1 #2 through #N are for national use.p& HHX HH7)  The STM1s are then byte interleaved to form an STMN, as described in section 2.2.2, and subsequently serialized and scrambled as described in section 2.4.p& HHX HH8)  The final operation is the calculation of a BIP8 code over the entire STMN bit stream on a frame by frame basis. The result is loaded into byte B1 of STM1 #1 in the following frame when the SOH is loaded. p& 3.HPointer 3.1HAU pointer HThe AU pointer provides a method of allowing flexible and dynamic alignment of the VC within the AU frame. HDynamic alignment means that the VC is allowed to "float" within the AU frame. Thus the pointer is able to accommodate differences not only in the phases of the VC and SOH, but in the frame rates as well. 3.1.1HAU pointer location HThe AU4 pointer is contained in bytes H1, H2 and H3 as shown in Figure3.1/G.709. The three individual AU32 pointers are contained in three separate H1, H2 and H3 bytes as shown in Figure 3.2/G.709. Likewise the four individual AU31 pointers are contained in four separate H1, H2 and H3 bytes as shown in Figure 3.3/G.709. 3.1.2HAU pointer value  N*ԌHThe pointer contained in H1 and H2 designates the location of the bytes where the VC begins. The two bytes allocated to the pointer function can be viewed as one word as shown in Figure 3.4/G.709. The last 10 bits (bits 716) of the pointer word carry the pointer value. The two S bits (bits 5 and 6) indicate the AU type. HAs illustrated in Figure 3.4/G.709, the AU4 pointer value is a binary number with a range of 0 to 782 which indicates the offset between the pointer and the first byte of the VC. As shown in Figure 3.1/G.709, the H1 and H2 bytes contain the pointer value while the position which the pointer indicates is the very first byte of the consecutive three bytes. Figure 3.4/G.709 also indicates two additional valid pointers; the Concatenation Indication (CI); and the Null Pointer Indication (NPI). The CI is indicated by "1001" in bits 14, bits 56 unspecified, and ten "1"s in bits 716, while the NPI is indicated by "1001" in bits 14, bits 56 unspecified, five "1"s in bits 711 followed by five "0"s in bits 1216. HAs illustrated in Figure 3.4/G.709, the AU32 pointer value is also a binary number with a range of 0 to 782. Since there are three AU32s in the STN1, each AU32 has its own associated H1, H2 and H3 bytes. As shown in Figure3.2/G.709, the H bytes are shown in sequence. The first H1, H2, H3 set refers to the first AU32, and the second set to the second AU32, and so on. The same is true for the information bytes. For the AU32s, each pointer operates independently. HLikewise, as illustrated in Figure 3.4/G.709, the AU31 pointer value is a binary number with a range of 0 to 581. Since there are four AU31s in the STM1, each AU31 has its own associated H1, H2 and H3 bytes. As shown in Figure 3.3/G.709, the H bytes are shown in sequence. The first H1. H2, H3 set refers to the first AU31, the second set to the second AU31, and so on. The same is true for the information bytes. For the AU31s each pointer operates independently. HIn all cases, the STM1 SOH and AU pointer bytes are not counted in the offset. For example, in an AU4, the pointer value of 0 indicates that the VC starts in the byte location that immediately follows the last H3 byte, whereas an offset of 87 indicates that the VC starts three bytes after the K2 byte. 3.1.3HFrequency justification HIf there is a frequency offset between the frame rate of the SOH and that of the VC, then the pointer value will be incremented or decremented as needed, accompanied by a corresponding positive or negative justification byte or bytes. Consecutive pointer operations must be separated by at least three frames (i.e. every fourth frame) in which the pointer value remains constant. HIf the frame rate of the VC is too slow with respect to that of the SOH, then the alignment of the VC must periodically slip back in time and the pointer value must be incremented by one. This operation is indicated by inverting bits 7, 9, 11, 13 and 15 (Ibits) of the pointer word to allow 5bit majority voting at the receiver. Three positive justification bytes appear immediately after the last H3 byte in the AU4 frame containing inverted Ibits. Subsequent pointers will contain the new offset. This is illustrated in Figure3.5/G.709. HFor AU32 frames, a positive justification byte appears immediately after the associated H3 byte of the individual AU32 frame containing inverted Ibits. Subsequent pointers will contain the new offset. This is illustrated in Figure 3.6/G.709. The same is true for AU31 as shown in Figure 3.7/G.709. HIf the frame rate of the VC is too fast with respect to that of the SOH, then the alignment of the VC must periodically be advanced in time and the pointer value must be decremented by one. This operation is indicated by inverting bits 8, 10, 12, N* 14 and 16 (Dbits) of the pointer word to allow 5bit majority voting at the receiver. Three negative justification bytes appear in the H3 bytes in the AU4 frame containing inverted Dbits. Subsequent pointers will contain the new offset. This is illustrated in Figure 3.8/G.709. HFor AU32 frames, a negative justification byte appears in the H3 byte of the individual AU32 frame containing inverted Dbits. Subsequent pointers will contain the new offset. This is illustrated in Figure 3.9/G.709. The same is true for AU31 as shown in Figure 3.10/G.709. 3.1.4HNew data flag HBits 14 (Nbits) of the pointer word carry a New Data Flag (NDF) which allows an arbitrary change of the pointer value if that change is due to a change in the payload. HFour bits are allocated to the flag to allow error correction. The decoding may be performed by accepting NDF enabled if at least three bits match. Normal operation is indicated by a "0110" code in the Nbits. NDF is indicated by inversion of the Nbits to "1001". The new alignment is indicated by the pointer value accompanying the NDF and takes effect at the offset indicated. NDF should be enabled when the pointer value transits between its normal value and the CI or NPI. 3.1.5HPointer generation HThe following summarizes the rules for generating the AU pointers. HHX HH1)  During normal operation, the pointer locates the start of the VC within the AU frame. The NDF is set to "0110".p& HHX HH2)  The pointer value can only be changed by operation 3, 4 or 5.p& HHX HH3)  If a positive justification is required, the current pointer value is sent with the Ibits inverted and the subsequent positive justification opportunity is filled with dummy information. Subsequent pointers contain the previous pointer value incremented by one. No subsequent increment or decrement operation is allowed for at least three frames following this operation.p& HHX HH4)  If a negative justification is required, the current pointer value is sent with the Dbits inverted and the subsequent negative justification opportunity is overwritten with actual data. Subsequent pointers contain the previous pointer value decremented by one. No subsequent increment or decrement operation is allowed for at least three frames following this operation.p& HHX HH5)  If the alignment of the VC changes for any reason other than rules 3 or 4, the new pointer value shall be sent accompanied by NDF set to "1001". The NDF only appears in the first frame that contains the new values. The new location of the VC begins at the first occurrence of the offset indicated by the new pointer. No subsequent increment or decrement operation is allowed for at least three frames following this operation.p& 3.1.6HPointer interpretation HThe following summarizes the rules for interpreting the AU pointers. HHX HH1)  During normal operation, the pointer locates the start of the VC within N* the AU frame.p& HHX HH2)  Any variation from the current pointer value is ignored unless a consistent new value is received three times consecutively or it is preceded by one of rules 3, 4 or 5.p& HHX HH3)  If the majority of the Ibits of the pointer word are inverted, a positive justification operation is indicated. Subsequent pointer values shall be incremented by one.p& HHX HH4)  If the majority of the Dbits of the pointer word are inverted, a negative justification operation is indicated. Subsequent pointer values shall be decremented by one.p& HHX HH5)  If the NDF is set to "1001", then the coincident pointer value shall replace the current one at the offset indicated by the new pointer value regardless of the state of the receiver.p& 3.2HTU3 pointers HThere are two types of TU3 pointers, TU31 and TU32. TU3 pointer provides a method of allowing flexible and dynamic alignment of VC3 within the TU3 frame, independent of the actual contents of the VC. Dynamic alignment means that the VC3 is allowed to "float" within the TU3 frame. 3.2.1HTU3 pointer location HThree individual TU32 pointers are contained in the three separate H1, H2 and H3 bytes as shown in Figure 3.11/G.709. Four individual TU31 pointers are contained in the four separate H1, H2 and H3 bytes as shown in Figure3.12/G.709. 3.2.2HTU3 pointer value HThe TU3 pointer value contained in H1 and H2 designates the location of the byte where the VC3 begins. The two bytes allocated to the pointer function can be viewed as one word as shown in Figure 3.4/G.709. The last ten bits (bits716) of the pointer word carry the pointer value. The two S bits (bits5 and 6) indicate the TU type. HThe TU32 pointer value is a binary number with a range of 0764 which indicates the offset between the pointer and the first byte of the VC32 as shown in Figure 3.11/G.709. HThe TU31 pointer value is a binary number with a range of 0581 which indicates the offset between the pointer and the first byte of the VC31 as shown in Figure 3.12/G.709. 3.2.3HFrequency justification HIf there is a frequency offset between the TU3 frame rate and that of the VC3, then the pointer value will be incremented or decremented as needed accompanied by a corresponding positive or negative justification byte. Consecutive pointer operations must be separated by at least three frames in which the pointer value remains constant. HIf the frame rate of the VC3 is too slow with respect to that of the TU3 frame rate, then the alignment of the VC must periodically slip back in time and the pointer must be incremented by one. This operation is indicated by inverting bits 7, N*  9, 11, 13 and 15 (Ibits) of the pointer word to allow 5bit majority voting at the receiver. A positive justification byte appears immediately after the individual H3 byte in the TU3 frame containing inverted Ibits. Subsequent TU3 pointers will contain the new offset. HIf the frame rate of the VC3 is too fast with respect to that of the TU3 frame rate, then the alignment of the VC must be periodically advanced in time and the pointer must be decremented by one. This operation is indicated by inverting bits 8, 10, 12, 14 and 16 (Dbits) of the pointer word to allow 5bit majority voting at the receiver. A negative justification byte appears in the individual H3 byte in the TU3 frame containing inverted Dbits. Subsequent TU3 pointers will contain the new offset. 3.2.4HNew data flag HBits 14 (Nbits) of the pointer word carry NDF which allows an arbitrary change of the value of the pointer if that change is due to a change in the VC3. HFour bits are allocated to the flag to allow for error correction. The decoding may be performed by accepting NDF enabled if at least three bits match. Normal operation is indicted by a "0110" code in the Nbits, NDF is indicated by inversion of the Nbits to "1001". The new alignment is indicated by the pointer value accompanying the NDF and takes effect at the offset indicated. 3.2.5HPointer generation HThe following summarizes the rules for generating the TU3 pointers. HHX HH1)  During normal operation, the pointer locates the start of the p& H VC3 within the TU3 frame. The NDF is set to "0110". HHX HH2)  The pointer value can only be changed by operation 3, 4 or 5.p& HHX HH3)  If a positive justification is required, the current pointer value is sent with the Ibits inverted and the subsequent positive justification opportunity is filled with dummy information. Subsequent pointers contain the previous pointer value incremented by one. No subsequent increment or decrement operation is allowed for at least three frames following this operation.p& HHX HH4)  If a negative justification is required, the current pointer value is sent with the Dbits inverted and the subsequent negative justification opportunity is overwritten with actual data. Subsequent pointers contain the previous pointer value decremented by one. No subsequent increment or decrement operation is allowed for at least three frames following this operation.p& HHX HH5)  If the alignment of the VC changes for any reason other than rules 3 or 4, the new pointer value shall be sent accompanied by the NDF set to "1001". The NDF only appears in the first frame that contains the new value. The new VC location begins at the first occurrence of the offset indicated by the new pointer. No subsequent increment or decrement operation is allowed for at least three frames following this operation.p& 3.2.6HPointer interpretation HThe following summarizes the rules for interpreting the TU3 pointers.  N* ԌHHX HH1)  During normal operation the pointer locates the start of the VC3 within the TU3 frame.p& HHX HH2)  Any variation from the current pointer value is ignored unless a consistent new value is received three times consecutively or it is preceded by one of rules 3, 4 or 5.p& HHX HH3)  If the majority of the Ibits of the pointer word are inverted, a positive justification is indicated. Subsequent pointer values shall be incremented by one.p& HHX HH4)  If the majority of the Dbits of the pointer word are inverted, a negative justification is indicated. Subsequent pointer values shall be decremented by one.p& HHX HH5)  If the NDF is set to "1001", then the coincident pointer value shall replace the current one at the offset indicated by the new pointer value regardless of the state of the receiver.p& 3.3HTU1/TU2 pointer HThe TU1 pointer is only used with floating mapping. Floating and locked modes of operation are described in section 5.2. HThe TU1 and TU2 pointers provide a method of allowing flexible and dynamic alignment of the VC1/VC2 within the TU1 and TU2 multiframes, independent of the actual contents of the VC. 3.3.1HTU1/TU2 pointer location HThe TU1/TU2 pointers are contained in the V1 and V2 bytes as illustrated in Figure 3.13/G.709. 3.3.2HTU1/TU2 pointer value HThe TU pointer word is shown in Figure 3.14/G.709. HThe pointer value (bits 716) is a binary number which indicates the offset from V2 to the first byte of the VC1/VC2. The range of the offset is different for each of the TU sizes as illustrated in Figure 3.15/G.709. Note that the pointer bytes are not counted in the offset calculation. 3.3.3HTU1/TU2 multiframe indication byte HTU1/TU2 multiframe indication byte (H4) relates to the lowest level of multiplexing structure and indicates a variety of different multiframes for use by certain payloads. Specifically it provides: H   500 s (4frame) multiframe identifying frames containing TU1/TU2 pointers in the floating TU1/TU2 mode, and reserved byte locations in the locked TU1 mode.p& H   2ms (16frame) multiframe for byte synchronous outslot signalling for 2048 kbit/s payloads in the locked TU1 mode.p& H   3 ms (24frame) multiframe for byte synchronous outslot signalling for 1544 kbit/s payloads in the locked TU1 mode.p& N* Ԍ HThe coding of the H4 byte is illustrated in Figure 3.16/G.709. HFor network elements that operate only in the floating TU1/TU2 mode, a simplified multiframe alignment byte may be used. The simplified version provides only the 500 s multiframe. The 2 or 3 ms multiframe of any signalling within floating TU1s is indicated by perTU multiframe indicators carried within the TU1. Figure 3.13/G.709 shows the VC1/VC2 mapping in the multiframed TU1/TU2. HA converter from locked to floating TUs is permitted to pass H4 through transparently. A converter from floating to locked TUs must recover and align the multiframes from all of the floating TUs and so can transmit any convenient full multiframe on the locked TU side. 3.3.4HTU1/TU2 frequency justification HThe TU1/TU2 pointer is used to frequency justify the VC1/VC2 exactly the same way that the TU3 pointer is used to frequency justify the VC3. A positive justification opportunity immediately follows the V3 byte. Additionally, V3 serves as the negative justification opportunity such that when the opportunity is taken, V3 is overwritten by data. This is also shown in Figure 3.15/G.709. The indication of whether or not a justification opportunity has been taken is provided by the I and Dbits of the pointer in the current TU multiframe. The value contained in V3 when not being used for a negative justification is not defined. The receiver is required to ignore the value contained in V3 whenever it is not used as negative justification. 3.3.5HTU1/TU2 sizes HBits 5 and 6 of TU1/TU2 pointer indicate the size of the TU. Four sizes are currently provided: 8   8 Size  Designation  TU pointer range  8    (in 500 s)  8 8  01  TU22  0571  8  00  TU21  0427  8  10  TU12  0139  8  11  TU11  0103  8   HNote that this technique is only used at the TU1/TU2 levels. 3.3.6HNew data flag HBits 14 (Nbits) of the pointer word carry a NDF. It is the mechanism which allows an arbitrary change of the value of a pointer, and possibly also the size of the TU, if that change is due to a change in the payload. If the change includes a change in size then, implicitly, there must be a simultaneous new data transition in all of the TUs in the TUG21. HAs with the TU3 pointer NDF, the normal value is "0110" (transmitted), and the value "1001" (received exactly) indicates a new alignment for the VC, and possibly new size. If a new size is indicted, then all TU pointers (1 to 4) in the TUG21 must simultaneously indicate NDF with the same new size. The new alignment, and possibly size, is indicated by the pointer value and size value accompanying the NDF and takes N*  effect at the offset indicated. The NDF should be enabled when the pointer value transits between its normal value and the CI. 3.3.7HTU concatenation HTU2s may be concatenated to form a TU2mc (concatenated m x TU2s) to carry payloads requiring a capacity of more than a C21 (for the TU21 case) or C22 (for the TU22 case) A CI ("1001" in bits 14, bits 56 unspecified, and all ones in bits 716 of the TU2 pointer) is used to show that this multi C2 payload, carried in a single CV2mc (concatenated m x VC2), must be kept together. HNote that the TU2 is carried in a TUG2 as shown in Figure 5.2/G.709 and Figure 5.3/G.709. HIf a TU2 pointer contains the concatenation indication, then the pointer processor determines that this TU2 is concatenated to the previous TU2, and all operations indicated by the previous TU2 pointer are to be performed on this TU2 as well. 3.3.8HTU pointer generation and interpretation HThe rules for generating and interpreting the TU1/TU2 pointer for the VC1/VC2 are an extension to the rules provided in sections 3.2.5 and 3.2.6 for the TU3 pointer with the following modifications: H1)  The term TU3 is replaced with TU1/TU2 and the term VC3 is replaced with VC1/VC2.p& H2)  Additional pointer generation rule 6: If the size of the TU within a TUG21 is to change, then an NDF, as described in p& H rule 5, is to be sent in all TUs of the new size in the group J