WPCL 2BJ|x ` H   x|@  @8'@8' Y  `  @  <AP IX142E AYY  `  @  <AP IX142E AYI (3291) I (3291)   3.XHRecommendation G.704 /SYNCHRONOUS FRAME STRUCTURES USED AT -PRIMARY AND SECONDARY HIERARCHICAL LEVELS 1.HGeneral   HThis Recommendation gives functional characteristics of interfaces associated with: H network nodes, in particular, synchronous digital multiplex equipment and digital exchanges in IDNs for telephony and ISDNs, and H PCM multiplexing equipment.  X HSection 2 deals with basic frame structures, including details of frame length, frame alignment signals, cyclic redundancy check procedures and other basic information. HSections 3 to 6 contain more specific information about how certain channels at 64 kbit/s and at other bit rates are accommodated within the basic frame structures described in section 2. HElectrical characteristics for these interfaces are defined in Recommendation G.703. Note 1 This Recommendation does not necessarily apply for those cases where the signals that cross the interfaces are devoted to nonswitched connections such as those for the transport of encoded wideband signals (e.g. broadcast TV signals or multiplexed sound programme signals which need not be individually routed via the ISDN), see also Annex A to Recommendation G.702. Note 2 The frame structures recommended in this Recommendation do not apply to certain maintenance signals such as the all ones signals transmitted during fault conditions or other signals transmitted during outofservice conditions. Note 3 Frame structures associated with digital multiplexing equipments using justification are covered in each corresponding equipment Recommendation. Note 4 Inclusion of channel structures at other bit rates than 64 kbit/s is a matter for further study. Recommendations G.761 and G.76x dealing with the characteristics of PCM/ADPCM transcoding equipment contain information about channel structures at 32 kbit/s. The more general use of those particular structures is the subject of further study. 2.HBasic frame structures 2.1HBasic frame structure at 1544 kbit/s 2.1.1HFrame length H193 bits, numbered 1 to 193. The frame repetition rate is 8 000 Hz. 2.1.2HFbit HThe first bit of a frame is designated an Fbit and is used for such purposes as frame alignment, performance monitoring and providing a data link. 2.1.3HAllocation of Fbit HTwo alternative methods as given in Tables 1/G.704 and 2/G.704 for allocation of Fbits are recommended. 2.1.3.1 Methods 124 frame multiframe HAllocation of the Fbit to the multiframe alignment signal, the CRC check bits and the data link is given in Table 1/G.704. 2.1.3.1.1Multiframe alignment signal HThe Fbit of every fourth frame forms the pattern 001011...001011. This multiframe alignment signal is used to identify where each particular frame is located within the multiframe in order to extract the cyclic redundancy check code, CRC6, and the data link information as well as to identify those frames that contain signalling (frames 6, 12, 18 and 24), if channel associated signalling is used. 2.1.3.1.2Cyclic redundancy check HThe CRC6 is a method of performance monitoring that is contained within the Fbit position of frames 2, 6, 10, 14, 18 and 22 of every multiframe (see Table1/G.704). HThe CRC6 message block check bits e1, e2, e3, e4, e5 and e6 are contained within multiframe bits 194, 966, 1738, 2510, 3282 and 4054 respectively, as shown in Table 1/G.704. The CRC6 Message Block (CMB) is a sequence of 4632 serial bits that is coincident with a multiframe. By definition, CMB N begins at bit position 1 of multiframe N and ends at bit position 4632 of multiframe N. The first transmitted CRC bit of a multiframe is the most significant bit of the CMB polynomial. HIn calculating the CRC6 bits, the Fbits are replaced by binary ones. All information in the other bit positions will be identical to the information in the corresponding multiframe bit positions. HThe checkbit sequence e1 through e6 transmitted in multiframe N+1 is the remainder after multiplication by x6 and then division (Modulo2) by the generator polynomial x6+x+1 of the polynomial corresponding to CMB N. The first check bit (e1) is the most significant bit of the remainder; the last check bit (e6) is the least significant bit of the remainder. Each multiframe contains the CRC6 check bits generated for the preceding CMB. HAt the receiver, the received CMB, with each Fbit having first been replaced by a binary one, is acted upon by the multiplication/division process described above. The resulting remainder is compared on a bitbybit basis with the CRC6 check bits contained in the subsequently received multiframe. The compared check bits will be identical in the absence of transmission errors. 2.1.3.1.34 kbit/s data link HBeginning with frame 1 of the multiframe (see Table 1/G.704) first bit of a frame is part of the 4 kbit/s data link. This data link provides a ) communication path between primary hierarchical level terminals and will contain data, an idle data link sequence or a loss of frame alignment alarm sequence. HThe format to be used for the transmission of data over the (m) bits of the data link is still under study. HThe idle data link pattern is also under study. HA loss of frame alignment alarm sequence is used when a loss of frame alignment (LFA) condition has been detected. After a loss of frame alignment condition is detected at local end A, and 16bit LFA sequence of 8 "ones" 8 "zeros" (1111111100000000) will be transmitted in the (m) bits of the 4 kbit/s data link continuously to remote end B. HJTABLE 1/G.704 8Multiframe structure for the 24 frame multiframeă +   +    Bit number(s) in   +   Fbit  in each channel   +    time slot   + Frame  + Number Bit number  Assignments  For*  For* Signalling*  + within within character signalling  channel  . multiframe multiframe àFAS DL CRC  signal  designation  + +  1  1   m   1 8    +          +  2  194    el  1 8    +          +  3  387   m   1 8    +          +  4  580  0    1 8    +          +  5  773   m   1 8    +          +  6  966    e2  1 7  8  A  +          +  7  1159   m   1 8    +          +  8  1352  0    1 8    +          +  9  1545   m   1 8    +          +  10  1738    e3  1 8    +          +  11  1931   m   1 8    +          +  12  2124  1    1 7  8  B  +          +  13  2317   m   1 8    +          +  14  2510    e4  1 8    +          +  15  2703   m   1 8    +          +  16  2896  0    1 8    +          +  17  3089   m   1 8    +          +  18  328    e5  1 7  8  C  +          +  19  3475   m   1 8    +          +  20  3668  1    1 8    +          +  21  3861   m   1 8    +          +  22  4054    e6  1 8    +          +  23  4247   m   1 8    +          +  24  42440  1    17  8  D  +   FAS:Frame Alignment Signal (....001011....) DL:4 kbit/s Data Link (message bits m) CRC:CRC6 Block Check Field (check bits e1 ... e6) * Only applicable in the case of channel associated signalling, ct. k6  3.1.3.2. 2.1.3.2 Method 2 12 frame multiframe HAllocation of the Fbit to frame alignment signal, multiframe alignment signal and signalling is given in Table2/G.704. JTABLE 2/G.704 P 9Allocation of fbit for the 12 frame multiframeă P P 3   3  Frame number  Frame alignment  Multiframe alignment  3   signal  signal or signalling  3 3  1  1   3     3  2   S  3     3  3  0   3     3  4   S  3   Note For multiframe structure see section 3.1.3.2.2. 2.2HBasic frame structure at 6312 kbit/s 2.2.1HFrame length HThe number of bits per frame is 789. The frame repetition rate is 8000Hz. 2.2.2HFbits HThe last five bits of a frame are designated as Fbits, and are used for such purposes as frame alignment, performance monitoring and providing a data link. 2.2.3HAllocation of Fbits HAllocation of the Fbits is given in Table 3/G.704. JTABLE 3/G.704 P FAllocation of Fbitsă P P 5   5    5   Bit number  5 Frame number   5   5   785  786  787  788  789  5 5  1  1  1  0  0  m  5        5  2  1  0  1  0  0  5        5  3  x  x  x  a  m  5        5  4  e1  e2  e3  e4  e5  5   Hm:data link bit Ha:remote end alarm bit (1 state = alarm, 0 state = no alarm) Hei:CRC5 check bit (i = 1 to 5) Hx:spare bits to be set at state 1 if not used 2.2.3.1 Frame alignment signal HThe frame and multiframe alignment signal is:110010100, and is carried on the Fbits in frames 1 and 2, excluding bit 789 of frame 1. 2.2.3.2 Cyclic redundancy check HThe cyclic redundancy check 5 (CRC5) message block (CMB) is a sequence of 3151 serial bits which starts at bit number 1 of frame number 1 and ends at bit number 784 of frame number 4. The CRC5 message block check bits e1, e2, e3, e4 and e5 occupy the last five bits of the multiframe as shown in Table 3/G.704. HThe checkbit sequence e1 through e5 transmitted in multiframe N is the remainder after multiplication by x5 and division (Modulo2) by the generator polynomial X5+X4+X2+1 of the polynomial corresponding to CMB N. The first check bit (e1) is the most significant bit of the remainder; the last check bit (e5) is the least significant bit of the remainder. Each multiframe contains the CRC 5 check bits generated for the corresponding CMB. HAt the receiver the incoming sequence of 3156 serial bits (i.e.,3151bits of CMB and 5 CRC bits), when divided by the generator polynomials, will result in a remainder of 00000 in the absence of transmission errors. 2.2.3.3 4 kbit/s data link HThe bit m shown in Table 3/G.704 is used as a data link bit. These bits provide 4 kbit/s data transmission capability associated the 6312 kbit/s digital path. 2.2.3.4 Remote end alarm indication HAfter a loss of frame alignment condition is detected at local end A, remote end alarm signal bit as shown in Table 3/G.704 will be transmitted to remote end B. 2.3HBasic frame structure at 2048 kbit/s 2.3.1HFrame length H256 bits, numbered 1 to 256. The frame repetition rate is 8000Hz. 2.3.2HAllocation of bits numbers 1 to 8 of the frame HAllocation of bits numbers 1 to 8 of the frame is shown in Table4a/G.704. ITABLE 4a/G.704 P =Allocation of bits 1 to 8 of the frameă ,ԌP P *   *  Bit          *  number  1  2  3  4  5  6  7  8  *           *  Alternate          *  frames          * *  Frame containing  Si  0  0  1  1  0  1  1  *  the frame  *  alignment signal  Note 1  Frame alignment signal  * *  Frame not containing  Si  1  A  Sa4  Sa5 Sa6 Sa7 Sa8  *  the frame alignment  *  signal  Note 1 Note 2 Note 3  Note 4  *   Note 1 Si Bits reserved for international use. One specific use is described in section2.3.3. Other possible uses may be defined at a later stage. If no use is realized, these bits should be fixed at 1 on digital paths crossing an international border. However, they may be used nationally if the digital path does not cross a border. Note 2 This bit is fixed at 1 to assist in avoiding simulations of the frame alignment signal. Note 3 A Remote alarm indication. In undistributed operation, O; in alarm condition, 1. Note 4 Sa4 to Sa8 additional spare bits whose use may be as follows: Hi)h  bits Sa4 to Sa8 may be recommended by CCITT for use in specific pointtopoint applications (e.g. transcoder equipments conforming to Recommendation G.761); Hii)  bit Sa4 may be recommended by CCITT as a messagebased data link for operations, maintenance and performance monitoring. This channel originates at the point where the frame is generated and terminates where the frame is broken down. This requires further study; HHX HHiii) bits Sa5 to Sa7 are for national usage where there is no demand on them for specific pointtopoint applications (see i) above). HBits Sa4 to Sa8 (where these are not used) should be set to "1" on links crossing an international border. 2.3.3HDescription of the CRC4 procedure in bit 1 of the frame 2.3.3.1 Special use of bit 1 of the frame: where there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability, then bit 1 should be used for a Cyclic Redundancy Check4 (CRC4) procedure as detailed below. Note Equipment incorporating the CRC4 procedure should be designed to be capable of interworking with equipment which does not incorporate the CRC procedure, with the option being manually selectable (e.g., by straps). For such interworking, bit 1 of the frame should be fixed at 1state in both directions (see Table4a/G.704, Note 1).  2.3.3.2 The allocation of bits 1 to 8 of the frame is shown in Table4b/G.704 for a complete CRC4 multiframe. 8LTABLE 4B/G.704 8S 8FCRC4 multiframe structureă 8S 8S 82   84  Submultiframe Frame  Bits 1 to 8 of the frame  83  (SMF) number 82    1  2  3  4  5  6  7  8  8,  8,    0  C1  0  0  1  1  0  1  1  8,    1  0  1  A Sa4 Sa5 Sa6 Sa7 Sa8  8,    2  C2  0  0  1  1  0  1  1  8,   I  3  0  1  A Sa4 Sa5 Sa6 Sa7 Sa8  8,    4  C3  0  0  1  1  0  1  1  8,    5  1  1  A Sa4 Sa5 Sa6 Sa7 Sa8  8,    6  C4  0  0  1  1  0  1  1  8,    7  0  1  A Sa4 Sa5 Sa6 Sa7 Sa8  8, Multiframe  8,    8  C1  0  0  1  1  0  1  1  8,    9  1  1  A Sa4 Sa5 Sa6 Sa7 Sa8  8,    10  C2  0  0  1  1  0  1  1  8,    11  1  1  A Sa4 Sa5 Sa6 Sa7 Sa8  8,   II  12  C3  0  0  1  1  0  1  1  8,    13  E  1  A Sa4 Sa5 Sa6 Sa7 Sa8  8,    14  C4  0  0  1  1  0  1  1  8,    15  E  1  A Sa4 Sa5 Sa6 Sa7 Sa8  8,   Key:E CRC4 error indication bits (see section 2.3.3.4). SA Spare bits (see Note 4 to Table 4a/G.704). C1, C2, C3, C4 Cyclic Redundancy Check4 (CRC4) bits H (see sections 2.3.3.4 and 2.3.3.5). A remote alarm indication (see Table 4a/G.704). 2.3.3.3 Each CRC4 multiframe, which is composed of 16 frames numbered 0 to 15, is divided into two 8 frame submultiframes (SMF), designated SMF I and SMFII signifying their respective order of occurrence within the CRC4 multiframe structure. The SMF is the Cyclic Redundancy Check4 (CRC4) block size (i.e., 2048 bits). HThe CRC4 multiframe structure is not related to the possible use of a multiframe structure in 64 kbit/s channel time slot 16 (see section5.1.3.2). 2.3.3.4 The use of bit 1 in 2048 kbit/s CRC4 multiframe HIn those frames containing the frame alignment signal (defined in section2.3.2), bit 1 is used to transmit the CRC4 bits. There are four CRC4 bits in each SMF designated C1, C2, C3 and C4. HIn those frames not containing the frame alignment signal (see section2.3.2), bit 1 is used to transmit the 6bit CRC4 multiframe alignment signal and two spare bits (E). HThe CRC4 multiframe alignment signal has the form 001011. HThe E bits should be used to indicate received errored submultiframes by setting the binary state of one E bit from "1" to "0" for each errored submultiframe. Any delay between the detection of an errored submultiframe and the setting of the E bit that indicates the error state must be less than 1 second. Note 1 The E bits will always be taken into account even if the SMF which contains them is found to be errored, since there is little likelihood that they will be errored. Note 2 In the short term, there may exist, equipments which do not use the Si bits; in this case the Si bits are set to binary 1. 2.3.3.5 4 kbit/s Cyclic Redundancy Check 2.3.3.5.1Multiplication/division process HA particular CRC4 word, located in SMF(N) say, is the remainder after multiplication by x4 and then division (modulo 2) by the generator polynomialx4 + x + 1, of the polynomial representation of SMF(N1). Note When representing the contents of the check block as a polynomial, the first bit in the block i.e., frame 0 bit 1 or frame 8 bit 1 should be taken as being the most significant bit. Similarly, C1 is defined to be the most significant bit of the remainder and C4 the least significant bit of the remainder. 2.3.3.5.2Encoding procedure Hi)h  the CRC4 bits in the SMF are replaced by binary zeros. Hii)  The SMF is then acted upon by the multiplication/division process referred to the above section 2.3.3.5.1. HHX HHiii) The remainder resulting from the multiplication/division process is stored ready for insertion into the respective CRC4 locations of the next SMF. Note The CRC4 bits thus generated do not affect the result of the multiplication/division process in the next SMF because, as indicated in i) above, the CRC4 bit positions in an SMF are initially set at 0 during the multiplication/division process. 2.3.3.5.3Decoding procedure Hi)h  A received SMF is acted upon by the multiplication/division process, referred to above in section 2.3.3.5.1 after having its CRC4 bits extracted and replaced by zeros. Hii)  The remainder resulting from this division process is then stored and subsequently compared on a bit by bit basis with the CRC bits received in the next SMF. HHX HHiii) If the remainder calculated in the decoder exactly corresponds to the CRC4 bits received in the next SMF, it is assumed that the checked SMF is error free. 2.4HBasic frame structure at 8448 kbit/s 2.4.1HFrame length HThe number of bits per frame is 1056. They are numbered from 1 to 1056. The frame repetition rate is 8000Hz. 2.4.2HFrame alignment signal HThe frame alignment signal is:11100110 100000 and occupies the bit positions 1 to 8 and 529 to 534. 2.4.3HService digits HBit 535 is used to convey alarm indication (bit 535 at 1 state = alarm; bit 535 at 0 state = no alarm). HBit 536 is left free for national use and should be fixed at 1 on paths crossing the international border. The same applies to bits 9 40 in the case of channelassociated signalling. 3.XHCharacteristics of frame structure carrying channels at various bit rates in 1544 kbit/s 3.1HInterface at 1544 kbit/s carrying 64 kbit/s channels 3.1.1HFrame structure 3.1.1.1 Number of bits per 64 kbit/s channel time slot HEight, numbered 1 to 8. 3.1.1.2 Number of 64 kbit/s channel time slots per frame HBits 2 to 193 in the basic frame carry 24 octet interleaved 64 kbit/s channel time slots, numbered 1 to 24. 3.1.1.3 Allocation of Fbit HRefer to section 2.1.3. 3.1.2HUse of 64 kbit/s channel time slots HEach 64 kbit/s channel time slot can accommodate e.g., a PCM encoded voiceband signal conforming to G.711 or data information with a bit rate up to 64 kbit/s. 3.1.3HSignalling HTwo alternative methods as given in sections 3.1.3.1 and 3.1.3.2 are recommended: 3.1.3.1 Common channel signalling HOne 64 kbit/s channel time slot is used to provide common channel signalling at a rate of 64 kbit/s. In the case of the 12frame multiframe method 2 above, the pattern of the Sbit may be arranged to carry common channel signalling at a rate of 4 kbit/s or a submultiple of this rate. 3.1.3.2 Common associated signalling 3.1.3.2.1Allocation of signalling bits for 24frame multiframe HAs can be seen in Table 1/G.704, there are four different signalling bits (A, B, C and D) in the multiframe. This channel associated signalling can provide four independent 333bit/s signalling channels designated A, B, C and D, two independent 667bit/s signalling channels designated A and B (see note) or one 1333bit/s signalling channel. Note When only four state signalling is required the AB signalling bits previously associated with frames 6 and 12 respectively should be mapped into ABCD signalling bits of frame 6, 12, 18 and 24 respectively as follows: A=A, B=B, C=A, D=B. In this case the ABCD signalling is the same as the AB signalling specified in section3.1.3.2.2 below. 3.1.3.2.2Allocation of signalling bits for 12frame multiframe HBased on agreement between the administrations involved, channel associated signalling is provided for intraregional circuits according to the following arrangement: HA multiframe comprises 12 frames as shown in Table 5/G.704. The multiframe alignment signal is carried on the Sbit as shown in the table. HFrames 6 and 12 are designated as signalling frames. The eight bit in each channel time slot is used in every signalling frame to carry the signalling associated with that channel. 8MTABLE 5/G.704 8S 8IMultiframe structureă 8/   8/   Frame Multiframe  Bit number(s) in each  Signalling  8/ Frame  alignment  alignment  channel time slot  channel  8/ number  signal  signal  designation  8/  (see Note 1)  (S bit) For character  For   (see Note 2)  8/     signal  signalling   8/ 8/  1  1   1 8    8/        8/  2   0  1 8    8/        8/  3  0   1 8    8/        8/  4   0  1 8    8/        8/  5  1   1 8    8/        8/  6   1  1 7  8  A  8/        8/  7  0   1 8    8/        8/  8   1  1 8    8/        8/  9  1   1 8    8/        8/  10   1  1 8    8/        8/  11  0   1 8    8/        8/  12   0  1 7  8  B  8/   8S Note 1 When the Sbit is modified to signal the alarm indications to the remote end, the Sbit in frame 12 is changed from state 0 to 1. Note 2 Channel associated signalling provides two independent 667bit/s signalling channels designated A and B or one 1333bit/s signalling channel. 3.2HInterface at 1544 kbit/s carrying 32 kbit/s channels time slot (Note) Note This interface provides for the carrying of 32 kbit/s information. The interface will be used between network nodes and will apply to primary rate multiplexing equipment, digital crossconnect equipment, transcoder and other equipment relevant to the network nodes. Switching in this case is assumed to take place on a 64 kbit/s basis. 3.2.1HFrame structure 3.2.1.1 Number of bits per 32kbit/s channel time slot HFour, number 1 to 4. 3.2.1.2 Number of 32 kbit/s channel time slot per frame HBits 2 to 193 in the basic frame can carry 4bit interleaved forty eight 32kbit/s channel time slots, numbered 1 to 48. 3.2.1.3 Allocation of Fbits HRefer to section 2.1.3. 3.2.2HUse of 32 kbit/s channel time slot HEach 32kbit/s channel time slot can accommodate an ADPCM encoded voiceband signal conforming to G.721 or data with a bit rate up to 32kbit/s. 3.2.3H384 kbit/s twelve channel time slot grouping 3.2.3.1 Structure of twelve channel time slot grouping HThe structure of the 11544kbit/s frame for 32kbit/s channel time slots shown in Table6/G.704 which is structured to provide four independent 384kbit/s twelve channel time slot groupings. These are numbered 14, and transmitted in numbered order starting with time slot grouping number1. HThe signalling grouping channels for time slot groupings 14, occupy time slots 12, 24, 36 and 48 respectively. Each time slot grouping can be independently configured for either situations requiring channel associated signalling or situations with no signalling requirement (e.g. external common signalling). (See section3.2.3.1.1.) 8MTABLE 6/G.704 8S 8032 kbit/s channel time slots frame structure for 1544 kbit/s interfaceă 8?Time slot grouping No. 1:123456789101112 8Q(SGC) 8;Time slot grouping No. 2:131415161718192021222324 8Q(SGC) 8;Time slot grouping No.3:252627282930313233343536 8Q(SGC) 8;Time slot grouping No. 4:373839404142434445464748 8Q(SGC) Note 1 Each time slot signifies 32 kbit/s channel. Note 2 The signalling grouping channel (SGC) occupies the twelfth 32 kbit/s time slot of each time slot grouping. Note 3 Definitions for time slot grouping and signalling grouping channel are shown in section3.2.3. 3.2.3.1.1Use of a 384kbit/s time slot grouping HUse of a 384kbit/s time slot grouping is categorized into two possible configurations: H when no signalling capabilities are required, a 384kbit/s time slot grouping can carry twelve 32kbit/s channel time slots; H when channel associated signalling capabilities are required, a 384kbit/s time slot grouping will consist of eleven 32kbit/s channel time slots and a 32kbit/s channel time slot defined as signalling grouping channel. 3.2.3.1.2Use of a signalling grouping channel HA signalling grouping channel is used for the transmission of channel associated ABCD signalling information, signalling grouping channel alarm information, the signalling grouping channel multiframe alignment signal, and CRC6 error detection information between network nodes. 3.2.4H32 kbit/s signalling grouping channel multiframe structure 3.2.4.1 Number of bits per 32kbit/s signalling grouping channel time slot HFour, numbers 1 to 4. 3.2.4.2 Bit allocation of 32kbit/s signalling grouping channel time slot HAllocated to the last four bits of each time slot grouping. 3.2.4.3 Multiframe structure HThe signalling grouping channel multiframe structure consists of 24 consecutive frames numbered from 1 to 24. Table7/G.704 shows the signalling grouping channel multiframe structure. 3.2.4.4 Signalling grouping channel multiframe alignment signal HBit 3 of the signal grouping channel, as shown in Table7, contains the signal grouping channel multiframe alignment signal used to associate the signalling bits in the signal grouping channel with the proper channels of the associated time slot grouping. Note The signal grouping channel multiframe alignment signal is independent of and different from the framing bit of the 1544kbit/s frame. 3.2.4.5 CRC6 error detection information for the time slot grouping HAn optional 2kbit/s CRC6 error detection code word may be transmitted in the bit position indicated by CRC1 through CRC6 in Table7/G.704. HThe CRC6 message block (CMB) is a sequence of 1152 serial bits that is coincident with a time slot grouping multiframe. By definition, CMBN begins at bit position 0 of time slot grouping multiframeN and ends at bit position 1151 of time slot grouping multiframe N. HThe checkbit sequence CRC1 through CRC6 transmitted in multiframe N+1 is the remainder after multiplication by X6, and then division (Modulo2) by the generator polynomial X6Ġ+X+1 of the polynomial corresponding to CMBN. The first check bit, CRC1, is the most significant bit of the remainder; the last check bit, CRC6, is the least significant bit. The time slot grouping channel is included in this calculation with bit4 of the time slot grouping channel being set to 1. 8MTABLE 7/G.704 8S 8632 kbit/s signalling grouping channel multiframe structureă Note 1 i = 1 for 12th 32 kbit/s channel time slot Hi = 12 for 24th 32 kbit/s channel time slot Hi = 25 for 36th 32 kbit/s channel time slot Hi = 37 for 48th 32 kbit/s channel time slot Note 2 (Ai, Bi, Ci, Di): ABCD signalling bits HMj: Signalling grouping channel alarm indication bits HSk: Spare bits Note 3 The signalling grouping channel provides ABCD signalling capability P%Qfor 11channels within each time slot grouping. HWhen not utilizing the option to transmit the CRC6 error detection signal, CRC1 through CRC6 shall be set to 1. 3.2.4.6 Signalling HTwo alternative methods as given in sections3.2.4.6.1 and 3.2.4.6.2 are recommended. 3.2.4.6.1Common channel signalling HRefer to section 3.1.3.1. Two successive 32kbit/s channel time slots are used for 64kbit/s common channel signalling transmission. 3.2.4.6.2Channel associated signalling HAs indicated in Table7/G.704, bits 1 and 2 of the signalling grouping channel convey the channel associated signalling information for the channels of the associated time slot grouping. HThe signalling grouping channel can provide four independent 333bit/s signalling channels designated ABCD, two independent 667bit/s signalling channels designated AB signalling, or one 1333bit/s signalling channel designated A. Where only AB signalling is used, the AB signalling is repeated for the CD positions respectively. Where only A signalling is used, the A signalling is repeated for the BCD positions respectively. 3.2.4.7 Signalling grouping channel alarm indication signals HAs indicated in Table7/G.704, the signalling grouping channel contains four alarm indication bits, M1, M2, M3 and M4. HM1 provides the capability to transmit through the interface a remote time slot grouping alarm indication of a failure in the opposite direction of transmission. HM2 provides the capability to transmit through the interface an indication of a failure in tributary input signals to the network node. HM3 provides the capability to transmit through the interface an indication of a failure in tributary output signals from the network node. HM4 is set to one whenever M1 and/or M2 and/or M3 are set to one. 3.2.5HSignal grouping channel unused bits HThe bits marks S in Table7/G.704 are currently unused and set to 1. The definition and allocation of the S bits are for further study. 3.2.6HLoss and recovery of signalling channel multiframe alignment HLoss of the signalling grouping channel multiframe alignment signal is declared when 2 out of 4 signalling grouping channel framing bits are in error. The rare occurrence of a single instantaneous slip of + or 11 frames is undetected by the twooutoffour algorithm. Signalling grouping channel multiframe alignment shall be declared when the correct sequence of 24 valid signalling grouping channel framing bits are detected beginning with the first frame of the multiframe. 3.3HInterface at 1544 kbit/s carrying n x 64 kbit/s HElectrical characteristics should follow RecommendationG.703. HThe time slot mapping to the 1544 kbit/s interface is for further study. 4.XHCharacteristics of frame structure carrying channels at various bit rates in 6312 kbit/s interface 4.1HInterface at 6312 kbit/s carrying 64 kbit/s channels 4.1.1HFrame structure 4.1.1.1 Number of bits per 64 kbit/s channel time slot HEight, numbered 1 to 8. 4.1.1.2 Number of 64 kbit/s channel time slots per frame HBits 1 to 784 in the basic frame carry 98 octet interleaved 64 kbit/s channel time slots, numbered 1 to 98. Five bits per frame (Fbits) are added at the end of the frame for the frame alignment signal and for other signals. 4.1.1.3 Allocation of the Fbits HRefer to Table 3/G.704. 4.1.2. Use of 64 kbit/s channel time slots HEach 64 kbit/s channel time slot can accommodate e.g., a PCM encoded voiceband signal conforming to RecommendationG.11 or data information with a bit rate up to 64 kbit/s. 64 kbit/s channel time slots 97, 98 may be used for signalling. 4.1.3HSignalling HTwo alternative methods as given in sections 4.1.3.1 and 4.1.3.2 are recommended: 4.1.3.1 Common channel signalling HUse of 64 kbit/s channel time slots 97 and 98 for common channel signalling is under study. 4.1.3.2 Channel associated signalling HBased on agreement between the administrations involved, channel associated signalling is provided for intraregional circuits according to the following arrangement: 4.1.3.2.1Allocation of signalling bit HSixteen signalling bits (bit positions 769 to 784) are designated as St1 to ST16. One STibit (i=1 to 16) accommodates signalling information corresponding to six channel time slots i, 16+i, 32+i, 48+i, 64+i and 80+i in a manner described in section4.1.3.2.2 below. 4.1.3.2.2Signalling multiframe structure HEach ST bit constitutes an independent signalling multiframe over eight frames as shown in Table 8/G.704. 8MTABLE 8/G.704 ,Ԍ8S 8DSignalling multiframe structureă 8S 8S 8-   86 Frame  n n+1 n+2 n+3 n+4 n+5 n+6 n+7  8. number          8- 8. Use of  Fs  S1  S2  S3  S4  S5  S6  Sp  8. ST bit 8.   (See Note 1)  (See Note 2) (See Note 4)  8-   Note 1 The Fs bit is either alternate 0, 1 or the following 48 bit digital pattern: HA10101101100000110011010100111001111011010000101 HFor the 48 bit digital pattern, the "A" bit is usually fixed to state 1 and is reserved for optional use. The pattern is generated according to the following primitive polynomial (refer to Recommendation X.50): HX7Ġ+X4Ġ+1. Note 2 Sj bit (j=1 to 6) carries channel associated signalling or maintenance information. When the 48 bit pattern is adopted as Fs frame alignment signal, each Sj bit (j=1 to 6) can be multiframed, as follows: HSj1, Sj2, , Sj12 HSj1 bit carries the following 16 bit frame alignment pattern generated according to the same primitive polynomial as for the 48 bit pattern. HA011101011011000. HThe "A" bit is usually fixed to 1 and is reserved for optional use. each Sji(i=2 to 12) bit carries channel associated signalling for subrate circuits and/or maintenance information. Note 3 ST bits (Fs, S1, ,S6, and Sp) all at state 1 indicates Alarm Indication Signal (AIS) for six 64 kbit/s channels. Note 4 The Sp bit is usually fixed to state 1. When backward AIS for six 64kbit/s channels is required to be sent, the SP bit is set to state 0. 4.2HInterfaces at 6312 kbit/s carrying other channels than 64 kbit/s HFor further study. 5.XHCharacteristics of frame structure carrying channels at various bit rates in 2048 kbit/s interface 5.1HInterface at 2048 kbit/s carrying 64 kbit/s channels 5.1.1HFrame structure 5.1.1.1 Number of bits per 64 kbit/s channel time slot HEight, numbered 1 to 8. 5.1.1.2 Number of 64 kbit/s channel time slots per frame HBits 1 to 256 in the basic frame carry 32 octet interleaved time slots numbered 0 to 31. 5.1.1.3 Allocation of the bits of 64 kbit/s channel time slot 0 HSee Table 4a/G.704, (section 2.3.2). 5.1.2HUse of other 64 kbit/s channel time slots HEach of the 64 kbit/s channel time slots 1 to 15 and 17 to 31 can accommodate e.g., a PCM encoded voiceband signal according to Recommendation G.711 or a 64 kbit/s digital signal. HThe 64 kbit/s channel time slot 16 may be used for signalling. If not needed for signalling, in some cases it may be used for a 64 kbit/s channel, in the same way as time slots 1 to 15 and 17 to 31. 5.1.3HSignalling HThe use of 64 kbit/s channel time slot 16 is recommended for either common channel or channel associated signalling as required. HThe detailed requirements for the organization of particular signalling systems will be included in the specifications for those signalling systems. 5.1.3.1 Common channel signalling HThe 64 kbit/s channel time slot 16 may be used for common channel signalling up to a rate of 64 kbit/s. The method of obtaining signal alignment will form part of the particular common channel signalling specification. 5.1.3.2 Channel associated signalling HThis paragraph contains the recommended arrangement for the use of the 64kbit/s capability of channel time slot 16 for channel associated signalling. 5.1.3.2.1Multiframe structure HA multiframe comprises 16 consecutive frames (whose structure is given in section 5.1.1 above) and these are numbered from 0 to 15. HThe multiframe alignment signal is 0000 and occupies digit time slots 1 to 4 of 64 kbit/s channel time slot 16 in frame 0. 5.1.3.2.2Allocation of 64 kbit/s channel time slot 16 HWhen 64 kbit/s channel time slot 16 is used for channel associated signalling, the 64 kbit/s capacity is submultiplexed into lowerrate signalling channels using the multiframe alignment signal as a reference. HDetails of the bit allocation are given in Table 9/G.704. 8MTABLE 9/G.704 8S 86Bit allocation of channel associated 64 kbit/s time slot 16ă 8Cfor channel associated signallingă 8S 8S 81   89 Time slot16 Time slot16 Time slot 16  Time slot 16  83  of frame 0  of frame 1  of frame 2  of frame 15  81 81  0000 xyxx  abcd  abcd  abcd  abcd   abcd  abcd  81          81   ch. 1 ch. 16  ch. 2 ch. 17  ch. 15 ch. 30  81   Note 1 Channel numbers refer to telephone channel numbers. 64/kbit/s channel time slots 1 to 15 and 17 to 31 are assigned to telephone channels numbered from 1 to 30. Note 2 This bit allocation provides four 500bit/s signalling channels designated a, b, c and d for each channel for telephone and other services. With this arrangement, the signalling distortion of each signalling channel introduced by the PCM transmission system, will not exceed 2 ms. Note 3 When bits b, c, or d are not used they should have the values: Hb=1 Hc=0 Hd=1 HIt is recommended that the combination 0000 of bits a, b, c and d should not be used for signalling purposes for channels 115. Note 4 x=spare bit, to be set at state 1 if not used.  ( HHy=bit used for alarm indication to the remote end. In undisturbed operation, 0; in an alarm condition, 1.  `  5.2HInterface at 2048 kbit/s carrying n x 64 kbit/s  ( HElectrical characteristics should follow Recommendation G.703 (see  h Note 4 of Preamble to G.703). For the accommodation of n x 64 kbit time slots in the 2048 kbit/s frame, two situations are envisaged. 5.2.1HOne n x 64 kbit/s signal on the tributary side of a multiplex equipment HTime slots of the 2048 kbit/s frame are filled as follows: HTS 0 according to  2.3/G.704; HTS 16 reserved for the accommodation, if required, of a 64 kbit/s H signalling channel. H If 2  n  15, TS 1 to TS n are filled with n x 64 kbit/s data HHX (see Figure 1(a)/G.704);  `    H If 15 < n  30, TS 1 to TS 15 and TS 17 to TS (n+1) are filled HHX with n x 64 kbit/s data (see Figure 1(b)/G.704);  `  H Remaining time slots are filled with all ones. A :FIGURE 1/G.704 A   5.2.2HOne or more n x 64 kbit/s signal on the multiplexed signal side of a  HHmultiplexing equipment  `   H HFor any one n x 64 kbit/s signal, time slots of the 2048 kbit/s frame are filled as follows: HTS 0 according to  2.3/G.704; HTS 16 reserved for the accommodation, if required, of a 64 kbit/s K#Lsignalling channel. HTS (x) of the 2048 kbit/s frame is designated as the time slot into which the first time slot of the n x 64 kbit/s is accommodated. H If x  15 and x + (n1)  15, or, if x  17 and x + (n1)  31, then the filling of time slots is from TS (x) to TS (x+n1) (see Figure 2(a) and 2(b)/G.704); H If x + (n1)  16, then the filling of time slots is from TS (x) to TS 15 and TS 17 to TS (x+n) (see Figure 2(c)/G.704);   Note Once one n x 64 kbit/s signal has been accommodated into the multiplexed signal, care should be taken in the interpretation of the above rules to ensure that further such signals only use the time slots which remain spare. Q Q JFIGURE 2/G.704 Q Q 6.XHCharacteristics of frame structure carrying channels at various bit bit O%Prates in 8448 kbit/s interface 6.1HInterface at 8448 kbit/s carrying 64 kbit/s channels 6.1.1HFrame structure 6.1.1.1 Number of bits per 64 kbit/s channel time slot HEight, numbered from 1 to 8. 6.1.1.2 Number of 64 kbit/s channel time slots per frame HBits 1 to 1056 in the basic frame carry 132 octet interleaved 64kbit/s channel time slots, numbered from 0 to 131. 6.1.2HUse of 64 kbit/s channel time slots HH6.1.2.1 64 kbit/s channel time slot assignment in case of channelassociated signalling 6.1.2.1.164 kbit/s channel time slots 5 to 32, 34 to 65, 71 to 98 and 100 to 131 are assigned to 120 telephone channels numbered from 1 to 120. 6.1.2.1.264 kbit/s channel time slot 0 and the first 6 bits in 64 kbit/s channel time slot 66 are assigned to framing: the remaining 2 bits in 64kbit/s channel time slot 66 are devoted to services. 6.1.2.1.364 kbit/s channel time slots 67 to 70 are assigned to channel associated signalling as covered in section 6.1.3.2 below. 6.1.2.1.464 kbit/s channel time slots 1 to 4, 33 are left free for national use. 6.1.2.2 64 kbit/s channel time slot assignment in case of common channel M$Nsignalling 6.1.2.2.164 kbit/s channel time slots 2 to 32, 34 to 65, 67 to 98 and 100 to 131 are available for 127 telephone, signalling or other service channels. By bilateral agreement between the administrations involved, 64 kbit/s channel time slot 1 may either be used to provide another telephone or service channel or left free for service purposes within a digital exchange. HThe 64 kbit/s channels corresponding to 64 kbit/s channel time slot 1 to 32, 34 to 65 (etc. as above) are numbered 0 to 127. 6.1.2.2.264 kbit/s channel time slot 0 and the first 6 bits in channel time slot 66 are assigned to framing, the remaining 2 bits in 64 kbit/s channel time slot 66 are assigned to service. 6.1.2.2.364 kbit/s channel time slots 67 to 70 are in descending order of priority available for common channel signalling as covered in section6.1.3.1 below. 6.1.2.2.464 kbit/s channel slot 33 is left free for national use. 6.1.3  Description of the CRC procedure in 64kbit/s channel time slot 99 HIn order to provide an endtoend quality monitoring of the 8Mbit/s link, a CRC6 procedure is used and the six bits C1 to C6 computed at the source location are inserted in bit positions 1 to 6 of the time slot 99 (Figure3/G.704). HIn addition, bit 7 of this time slot, denoted E, is used to transmit an indication about the received signal in the opposite direction, whether the most recent CRC block has been received with errors or not. HThe CRC6 bits C1 to C6 are computed for each frame. The CRC6 block size is then 132 octets, i.e. 1056bits, and the computation is made 8000 times per second. F C1 C2 C3 C4 C5 C6 E S  >   Nbit 18 Q Q Q JFIGURE 3/G.704 Q KTime slot 99ă 6.1.3.1Multiplication division process HA given C1 C6 word located in frame N is the remainder after multiplication by X6 and then division (modulo 2) by the generator polynomial X6Ġ+X+1 of the polynomial representation of frame (N1). Note When representing the contents of a frame as a polynomial, the first bit in the frame should be taken as being the most significant bit. Similarly C1 is defined to be the most significant bit of the remainder and C6 the least significant bit of the remainder. 6.1.3.2Encoding procedure 6.1.3.2.1The CRC bit positions are initially set at 0 i.e.: H C1 = C2 = C3 = C4 = C5 = C6 = 0 6.1.3.2.2The frame is then acted upon by the multiplication/division process referred to above in 6.1.3.1. 6.1.3.2.3The remainder resulting from the multiplication/division process is stored ready for insertion into the respective CRC locations at the next frame. Q (Note These CRC bits do not affect the computation of the CRC bits in the next frame since the corresponding locations are set at zero before the computation. 6.1.3.3Decoding procedure 6.1.3.3.1A received frame is acted upon by the multiplication/division process, referred to above in section 6.1.3.1 after having its CRC bits extracted and replaced by zeros. 6.1.3.3.2The remainder resulting from this multiplication/division process is then stored and subsequently compared on a bit by bit basis with the CRC received in the next frame. 6.1.3.3.3If the decoder calculated remainder exactly corresponds to the CRC bits sent from the encoder, it is assumed that the checked frame is error free. 6.1.3.4Action on bit E HBit E of frame N is set at 1 in the transmitting direction is bits C16 detected in the most recent frame in the opposite direction have been found in error (at least one bit in error). In the opposite case it is set at zero. 6.1.4HSignalling HThe use of channel time slots 67 to 70 is recommended for either common channel or channelassociated signalling as required. The detailed requirements for the organization of particular signalling systems will be included in the specifications for those signalling systems. 6.1.4.1 Common channel signalling H64 kbit/s channel time slots 67 to 70 may be used for common channel signalling in a descending order of priority up to a rate of 64 kbit/s. The method of obtaining signal alignment will form part of the particular common channel signalling specification. 6.1.4.2 Channel associated signalling HThe Recommendation arrangement for the use of the 64 kbit/s capacity each 64 kbit/s channel time slot 67 to 70 for channelassociated signalling is as follows: 6.1.4.2.1 Multiframe structure HA multiframe for each 64 kbit/s bitstream comprises 16 consecutive frames (whose structure is given in section 6.1.1 above) and these are numbered from 0 to 15. HThe multiframe alignment signal is 0000 and occupies digit time slots 1 to 4 of channel time slots 67 to 70 in frame 0. 6.1.4.2.2Allocation of 64 kbit/s channel time slots 67 to 70 HWhen 64 kbit/s channel time slots 67 to 70 are used for channel associated signalling the 64 kbit/s capacity of each of the four 64 kbit/s channel time slots is submultiplexed into lower rate signalling channels using the multiframe alignment signal as a reference. Details of the bit allocation are given in Table 10/G.704. JTABLE 10/G.704 Q 6Bit allocation of 64 kbit/s channel time slots 67 to 70ă Q Q *   0 64 kbit/s      *  Channel  67  68  69  70  *  time slot      *       * Frame      * *  0  0000xyxx  0000xyxx  0000xyxx  0000xyxx  * 2  abcd abcd abcd abcd abcd abcd abcd abcd  L 1          +   ch.1  ch.16  ch.31  ch.46  ch.61  ch.76  ch.91 ch.106  * *  :  :  :  :  :  :  :  :  :  * *   abcd  abcd  abcd  abcd  abcd  abcd  abcd  abcd  K 15          *   ch.15  ch.30  ch.45  ch.60  ch.75  ch.90 ch.105 ch.120  *   Note 1 Channel numbers refer to telephone channel numbers. Refer to section6.1.2.1.1 for the assignment of 64 kbit/s channel time slots to the telephone channels. Note 2 This bit allocation provides four 500bit/s signalling channels designated a, b, c and d for each channel for telephone and other services. With this arrangement, the signalling distortion of each signalling channel introduced by the PCM transmission system, will not exceed +2 ms. Note 3 When bits b, c or d are not used they should have the value: Hb=1 Hc=0 Hd=1 HIt is recommended that the combination 0000 of bits a, c, c and d should not be used for signalling purposes for channels 115, 3145, 6175 and 91125. Note 4 x = spare bit, to be set at state 1 if not used. Hy = bit used for alarm indication to the remote end. In undisturbed K#Loperation, 0; in an alarm condition, 1. 6.2HInterface at 8448 kbit/s carrying other channels than 64 kbit/s HFor further study. OAnnexă Q E(to Recommendation G.704) Q 7Examples of CRC Implementations using sift registersă Ha)h  CRC6 procedure for interface at 1544 kbit/s (Reference:section2.1.3.1.2) Input: CMB N with F bits set to 1Generator polynomial: x6Ġ+x+1 Insert Figure here T180227086 HAt I, the CMB is fed serially (i.e. bit by bit) into the circuit, starting with bit number 1 of the multiframe (see Table 1/G.704). When the last bit of the CMB (i.e., bit number 4632 within the multiframe 4632) has been fed into the shift register, the CRC bits e1 to e6 are available at the outputs 1 to 6. (Output 1 provides the most significant bit, e1, and output 6 the least significant bit, e6.) Bits e1 to e6 are transmitted in the next CMB (c.f. Table 1/G.704). Note The outputs (1 to 6) of the shift register stages are reset to 0 after each CMB. Hb)h  CRC5 procedure for interface at 6312 kbit/s (Reference:section2.2.3.2) Input:CMBNGenerator polynomial:x5 + x4 + x2 + 1 Insert Figure here T1800228086 HAt I, the CMB is fed serially (i.e., bit by bit) into the circuit, starting with bit number 1 of frame number 1 (see Table 3/G.704). When the last bit of the CMB (i.e., bit number 784 of frame number 4) has been fed into the shift register, the CRC bits e1 to e5 are available at the outputs 1 to 5. (Output 1 provides the most significant bit, e1 and output 5 the least significant bit e5.) Bits e1 to e5 are transmitted in the corresponding multiframe (see Table 3/G.703). Note The outputs (1 to 5) of the shift register stages are reset to 0 after each CMB. Hc)h  CRC4 procedure for interface at 2048 kbit/s (Reference:section2.3.3.5) Input: SMF(N) with C1=C2=C3=C4 set to 0Generator polynomial: x4Ġ+x+1 BInsert Figure here T1800229086 HAt I, the SMF is fed serially (i.e., bit by bit) into the circuit, starting with bit C1=0 (see Table 4b/G.704). When the last bit of the SMF (i.e., bit number 256 of frame number 7, respectively of frame number 15) has been fed into the shift register, the CRC bits B1 to C4 are available at the outputs 1 to 4. (Output 1 provides the most significant bit, C1, and output 4 the least significant bit, C4.) Bits C1 to C4 are transmitted in the next SMF, i.e., SMF(N+1). Note The outputs (1 to 4) of the shiftregister stages are reset to 0 after each SMF. Q