$Suite $ITEX_MP $SuiteId af_test_0067_001 $SuiteOverviewPart $Begin_SuiteStructure $SuiteId af_test_0067_001 $StandardsRef /* ITU-T Recommendation Q.2110, Service Specific Connection Oriented Protocol(SSCOP) */ $PICSref /* ITU-T Recommendation Q.2110, Annex B */ $PIXITref /* ATM Forum/af-test-0067.001, Conformance ATS for SSCOP, Annex A */ $TestMethods /* Remote Single Layer Embedded Test Method */ $Comment /* */ $Structure&Objectives $Structure&Objective $TestGroupRef af_test_0067_001/PC/ $SelectExprId $Objective /* Protocol Capabilities */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_1/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_2/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_4/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_5/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_5/INOP/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_7/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_10/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/PC/STATE_10/INOP/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/SP/ $SelectExprId $Objective /* System Parameters */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $SelectExprId $Objective /* */ $End_Structure&Objective $Structure&Objective $TestGroupRef af_test_0067_001/SP/PARAM/ $SelectExprId $Objective /* */ $End_Structure&Objective $End_Structure&Objectives $Comment /* */ $End_SuiteStructure $Begin_TestCaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestCaseId S1_V_A1 $SelectExprId $Description /* Verify that the IUT generates the BGN PDU on demand at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestCaseId S1_V_P1 $SelectExprId $Description /* Verify that the IUT goes to state 3, if power-up robustness is implemented, or sends a BGREJ PDU, if not , on reception of retransmitted BGN PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestCaseId S1_V_P2 $SelectExprId $Description /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestCaseId S1_V_P5 $SelectExprId $Description /* Verify that the IUT sends a ENDAK PDU on reception of a END PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestCaseId S1_V_P6 $SelectExprId $Description /* Verify that the IUT ignores a ENDAK PDU and remains at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestCaseId S1_V_P16 $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestCaseId S1_V_P17 $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I1 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I2 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I3 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I4 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I6 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I10 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I14 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I15 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I16 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I17 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I18 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I19 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I20_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I20_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I21 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I22_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I22_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I23_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I23_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I24_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I24_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I25 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I26_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I26_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I27_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I27_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I28_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I28_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I29 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I30 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestCaseId S1_IV_I31 $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P3 $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a BGAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P4 $SelectExprId $Description /* Verify that the IUT ignores a BGREJ PDU and remains at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P8 $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a RS PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P9 $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a RSAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P10 $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a ER PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P11 $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a ERAK PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P12 $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a SD PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P13 $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a POLL PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P14 $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a STAT PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestCaseId S1_IO_P15 $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a USTAT PDU at state 1. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_A3 $SelectExprId $Description /* Verify that the IUT generates the END PDU on demand at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P1 $SelectExprId $Description /* Verify that the IUT ignores a retransmitted BGN PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P2 $SelectExprId $Description /* Verify that the IUT sends a BGAK PDU on reception of BGN PDU and goes to state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P3 $SelectExprId $Description /* Verify that the IUT goes to state 10 on reception of BGAK PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P4 $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P5 $SelectExprId $Description /* Verify that the IUT ignores a END PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P6 $SelectExprId $Description /* Verify that the IUT ignores a ENDAK PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P8 $SelectExprId $Description /* Verify that the IUT ignores a RS PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P9 $SelectExprId $Description /* Verify that the IUT ignores a RSAK PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P10 $SelectExprId $Description /* Verify that the IUT ignores a ER PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P11 $SelectExprId $Description /* Verify that the IUT ignores a ERAK PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P12 $SelectExprId $Description /* Verify that the IUT ignores a SD PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P13 $SelectExprId $Description /* Verify that the IUT ignores a POLL PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P14 $SelectExprId $Description /* Verify that the IUT ignores a STAT PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P15 $SelectExprId $Description /* Verify that the IUT ignores a USTAT PDU and remains at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P16 $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestCaseId S2_V_P17 $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I1 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I2 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I3 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I4 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I6 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I10 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I14 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I15 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I16 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I17 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I18 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I19 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I20_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I20_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I21 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I22_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I22_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I23_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I23_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I24_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I24_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I25 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I26_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I26_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I27_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I27_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I28_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I28_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I29 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I30 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestCaseId S2_IV_I31 $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 2. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_A1 $SelectExprId $Description /* Verify that the IUT generates the BGN PDU on demand at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P1 $SelectExprId $Description /* Verify that the IUT sends a BGAK and END PDU on reception of retransmitted BGN PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P2 $SelectExprId $Description /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P3 $SelectExprId $Description /* Verify that the IUT ignores a BGAK PDU and remains at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P4 $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P5 $SelectExprId $Description /* Verify that the IUT sends a ENDAK PDU on reception of a END PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P6 $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of ENDAK PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P8 $SelectExprId $Description /* Verify that the IUT ignores a RS PDU and remains at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P9 $SelectExprId $Description /* Verify that the IUT ignores a RSAK PDU and remains at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P10 $SelectExprId $Description /* Verify that the IUT ignores a ER PDU and remains at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P11 $SelectExprId $Description /* Verify that the IUT ignores a ERAK PDU and remains at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P12 $SelectExprId $Description /* Verify that the IUT ignores a SD PDU and remains at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P13 $SelectExprId $Description /* Verify that the IUT ignores a POLL PDU and remains at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P14 $SelectExprId $Description /* Verify that the IUT ignores a STAT PDU and remains at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P15 $SelectExprId $Description /* Verify that the IUT ignores a USTAT PDU and remains at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P16 $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestCaseId S4_V_P17 $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I1 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I2 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I3 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I4 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I6 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I10 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I14 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I15 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I16 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I17 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I18 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I19 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I20_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I20_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I21 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I22_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I22_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I23_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I23_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I24_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I24_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I25 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I26_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I26_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I27_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I27_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I28_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I28_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I29 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I30 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestCaseId S4_IV_I31 $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 4. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_A3 $SelectExprId $Description /* Verify that the IUT generates the END PDU on demand at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P1 $SelectExprId $Description /* Verify that the IUT sends a BGAK and RS PDU on reception of retransmitted BGN PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P2 $SelectExprId $Description /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 5 */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P3 $SelectExprId $Description /* Verify that the IUT ignores a BGAK PDU and remains at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P5 $SelectExprId $Description /* Verify that the IUT sends a ENDAK PDU on reception of a END PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P7 $SelectExprId $Description /* Verify that the IUT ignores a retransmitted RS PDU and remains at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P8 $SelectExprId $Description /* Verify that the IUT sends a RSAK PDU on reception of RS PDU and goes to state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P9 $SelectExprId $Description /* Verify that the IUT goes to state 10 on reception of RSAK PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P10 $SelectExprId $Description /* Verify that the IUT ignores a ER PDU and remains at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P11 $SelectExprId $Description /* Verify that the IUT ignores a ERAK PDU and remains at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P12 $SelectExprId $Description /* Verify that the IUT ignores a SD PDU and remains at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P13 $SelectExprId $Description /* Verify that the IUT ignores a POLL PDU and remains at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P14 $SelectExprId $Description /* Verify that the IUT ignores a STAT PDU and remains at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P15 $SelectExprId $Description /* Verify that the IUT ignores a USTAT PDU and remains at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P16 $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestCaseId S5_V_P17 $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I1 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I2 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I3 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I4 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I6 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I10 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I14 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I15 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I16 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I17 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I18 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I19 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I20_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I20_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I21 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I22_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I22_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I23_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I23_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I24_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I24_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I25 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I26_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I26_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I27_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I27_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I28_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I28_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I29 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I30 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestCaseId S5_IV_I31 $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INOP/ $TestCaseId S5_IO_P4 $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_5/INOP/ $TestCaseId S5_IO_P6 $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of ENDAK PDU at state 5. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P2 $SelectExprId $Description /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P5 $SelectExprId $Description /* Verify that the IUT sends a ENDAK PDU and goes to state 1 on reception of a END PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P8 $SelectExprId $Description /* Verify that the IUT goes to state 6 on reception of RS PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P11 $SelectExprId $Description /* Verify that the IUT sends a ERAK PDU and goes to state 8 on reception of a ER PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P12 $SelectExprId $Description /* Verify that the IUT goes to state 8 on reception of ERAK PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P19 $SelectExprId $Description /* Verify that the IUT ignores a SD PDU and remains at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P21 $SelectExprId $Description /* Verify that the IUT ignores a POLL PDU and remains at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P26 $SelectExprId $Description /* Verify that the IUT ignores a STAT PDU and remains at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P36 $SelectExprId $Description /* Verify that the IUT ignores a USTAT PDU and remains at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P40 $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestCaseId S7_V_P41 $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I1 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I2 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I3 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I4 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I6 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I10 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I14 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I15 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I16 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I17 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I18 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I19 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I20_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I20_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I21 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I22_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I22_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I23_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I23_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I24_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I24_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I25 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I26_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I26_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I27_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I27_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I28_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I28_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I29 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I30 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestCaseId S7_IV_I31 $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestCaseId S7_IO_P1 $SelectExprId $Description /* Verify that the IUT ignores a retransmitted BGN PDU and remains at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestCaseId S7_IO_P3 $SelectExprId $Description /* Verify that the IUT ignores a BGAK PDU and remains at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestCaseId S7_IO_P4 $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestCaseId S7_IO_P6 $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of ENDAK PDU at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestCaseId S7_IO_P7 $SelectExprId $Description /* Verify that the IUT ignores a retransmitted RS PDU and remains at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestCaseId S7_IO_P9 $SelectExprId $Description /* Verify that the IUT ignores a RSAK PDU and remains at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestCaseId S7_IO_P10 $SelectExprId $Description /* Verify that the IUT ignores a retransmitted ER PDU and remains at state 7. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_A3 $SelectExprId $Description /* Verify that the IUT, at state 10, generates the END PDU on demand. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_A5 $SelectExprId $Description /* Verify that the IUT, at state 10, generates the RS PDU on demand. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P1 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a BGAK PDU on reception of a retransmitted BGN PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P2 $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 3 on reception of BGN PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P3 $SelectExprId $Description /* Verify that the IUT, at state 10, ignores a BGAK PDU and remains. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P5 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ENDAK PDU and goes to state 1 on reception of a END PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P7 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a RSAK PDU on reception of a retransmitted RS PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P8 $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 6 on reception of RS PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P9 $SelectExprId $Description /* Verify that the IUT, at state 10, ignores a RSAK PDU and remains. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P10 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ERAK PDU on reception of a retransmitted ER PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P11 $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 9 on reception of ER PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P12 $SelectExprId $Description /* Verify that the IUT, at state 10, ignores a ERAK PDU and remains. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P13 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a USTAT PDU on reception of SD PDU out of the window. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P14 $SelectExprId $Description /* Verify that the IUT, at state 10, ignores a SD PDU that is out of the window when window is not available. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P15 $SelectExprId $Description /* Verify that the IUT, at state 10, saves the next highest expected SD PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P17 $SelectExprId $Description /* Verify that the IUT, at state 10, saves a SD PDU that sequence number is between the sequence number of the next in sequence and the next highest expected SD PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P18 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ER PDU on reception of a SD PDU that sequence number is between the sequence number of the next in sequence and the next highest expected SD PDUs and is already in RX BUFFER. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P19 $SelectExprId $Description /* Verify that the IUT, at state 10, accepts the next in sequence SD PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P21 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ER PDU on reception of a POLL PDU that sequence number is less than that of the next highest expected SD PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P22 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a STAT PDU on reception of a POLL PDU that sequence number is greater than that of the next highest expected SD PDU and is out of the window. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P23_1 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a STAT PDU on reception of a POLL PDU that sequence number is greater than that of the next highest expected SD PDU and is out of the window. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P23_2 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a STAT PDUs(with segmenting) on reception of a POLL PDU that sequence number is greater than that of the next highest expected SD PDU and is out of the window. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P24 $SelectExprId $Description /* Verify that the IUT, at state 10 and having no missing gap of received SD PDUs, sends a STAT PDU on reception of a POLL PDU that sequence number is less than or equal to that of the next highest expected SD PDU and is within the window. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P25 $SelectExprId $Description /* Verify that the IUT, at state 10 and having a missing gap of received SD PDUs, sends a STAT PDU on reception of a POLL PDU that sequence number is less than or equal to that of the next highest expected SD PDU and is within the window. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P26 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a STAT PDU that poll sequence number is incorrect. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P27 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a STAT PDU that poll sequence number is correct but SD PDU sequence number is incorrect. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P32 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a STAT PDU that poll sequence number and SD PDU sequence number are correct but its list element has incorrect sequence number. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P33 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a STAT PDU that poll sequence number and SD PDU sequence number are correct but its list elements are not increasing order. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P38_1 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a USTAT PDU that list element has incorrect sequence number. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P38_2 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a USTAT PDU that list elements are not increasing order. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P39 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a USTAT PDU that list elements are not increasing order. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P40 $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestCaseId S10_V_P41 $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I1 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I2 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I3 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I4 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I6 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I10 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I14 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I15 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I16 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I17 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I18 $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I19 $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I20_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I20_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I21 $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I22_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I22_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I23_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I23_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I24_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I24_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I25 $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I26_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I26_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I27_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I27_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I28_1 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I28_2 $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I29 $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I30 $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestCaseId S10_IV_I31 $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 10. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INOP/ $TestCaseId S10_IO_P4 $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 1 on reception of BGREJ PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/PC/STATE_10/INOP/ $TestCaseId S10_IO_P6 $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 1 on reception of ENDAK PDU. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestCaseId S2_CC_T1 $SelectExprId $Description /* Verify that the IUT, at state 2, sends a END PDU and goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestCaseId S4_CC_T1 $SelectExprId $Description /* Verify that the IUT, at state 4, goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestCaseId S5_CC_T1 $SelectExprId $Description /* Verify that the IUT, at state 5, sends a END PDU and goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestCaseId S7_CC_T1 $SelectExprId $Description /* Verify that the IUT, at state 7, sends a END PDU and goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestCaseId S10_POLL_T3 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a POLL PDU when the Timer Timer_POLL is expired. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestCaseId S10_KEEP_ALIVE_T4 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a POLL PDU when the Timer Timer_KEEP_ALIVE is expired. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestCaseId S10_IDLE_T5 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a POLL PDU when the Timer Timer_IDLE is expired. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestCaseId S10_NO_RESPONSE_T6 $SelectExprId $Description /* Verify that the IUT, at state 10, sends a END PDU when the Timer Timer_NO_RESPONSE is expired. */ $End_CaseIndex $CaseIndex $TestGroupRef af_test_0067_001/SP/PARAM/ $TestCaseId SP3_MaxPD $SelectExprId $Description /* Check the value of MaxPD system parameter(Maximum number of SD PDUs before transmission of a POLL PDU). */ $End_CaseIndex $Comment /* */ $End_TestCaseIndex $Begin_TestStepIndex $StepIndex $TestStepRef af_test_0067_001/GENERAL/ $TestStepId TS_Wait $Description /* Test Step of alternatives OTHERWISE, and TIMEOUT of T_Wait. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/GENERAL/ $TestStepId TS_Opr $Description /* Test Step of alternatives OTHERWISE, and TIMEOUT of T_Opr. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/GENERAL/ $TestStepId TS_CC $Description /* Test Step of alternatives OTHERWISE, and TIMEOUT of Timer_CC. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/GENERAL/ $TestStepId RESTORE_SEQUENCE $Description /* */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/PROCEDURE/ $TestStepId Initialize_State_Variables $Description /* Procedure used to initialize state variables when new connection is established. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/ $TestStepId postamble $Description /* Procedure used to place the IUT at state 1. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/PREAMBLE/ $TestStepId S1_PREAMBLE $Description /* Procedure used to place the IUT at state 1 from any state. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/PREAMBLE/ $TestStepId S2_PREAMBLE $Description /* Procedure used to place the IUT at state 2 from any state. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/PREAMBLE/ $TestStepId S4_PREAMBLE $Description /* Procedure used to place the IUT at state 4 from any state. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/PREAMBLE/ $TestStepId S5_PREAMBLE $Description /* Procedure used to place the IUT at state 5 from any state. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/PREAMBLE/ $TestStepId S7_PREAMBLE $Description /* Procedure used to place the IUT at state 7 from any state. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/PREAMBLE/ $TestStepId S10_PREAMBLE $Description /* Procedure used to place the IUT at state 10 from any state. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/VERIFY/ $TestStepId S1_VERIFY $Description /* Procedure used to verify that the IUT is at state 1. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/VERIFY/ $TestStepId S2_VERIFY $Description /* Procedure used to verify that the IUT is at state 2. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/VERIFY/ $TestStepId S4_VERIFY $Description /* Procedure used to verify that the IUT is at state 4. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/VERIFY/ $TestStepId S5_VERIFY $Description /* Procedure used to verify that the IUT is at state 5. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/VERIFY/ $TestStepId S7_VERIFY $Description /* Procedure used to verify that the IUT is at state 7. */ $End_StepIndex $StepIndex $TestStepRef af_test_0067_001/VERIFY/ $TestStepId S10_VERIFY $Description /* Procedure used to verify that the IUT is at state 10. */ $End_StepIndex $Comment /* */ $End_TestStepIndex $End_SuiteOverviewPart $DeclarationsPart $TS_TypeDefs $ASN1_TypeDefs $Begin_ASN1_TypeDef $ASN1_TypeId LIST_ELEMENT_TYPE $Comment /* Used for STAT PDU Type definition */ $ASN1_TypeDefinition SEQUENCE { pAD OCTET STRING(SIZE (1..1)), lE BIT STRING(SIZE (24..24)) } $End_ASN1_TypeDefinition $Comment /* */ $End_ASN1_TypeDef $Begin_ASN1_TypeDef $ASN1_TypeId LIST_TYPE $Comment /* Used for STAT PDU Type definition */ $ASN1_TypeDefinition SEQUENCE OF LIST_ELEMENT_TYPE $End_ASN1_TypeDefinition $Comment /* */ $End_ASN1_TypeDef $End_ASN1_TypeDefs $End_TS_TypeDefs $TS_OpDefs $Begin_TS_OpDef $TS_OpId GET_VR_MR $TS_OpResult INTEGER $TS_OpDescription /* This operation is used to set the Maximum acceptable Receive state value(VR(MR)). Updating VR(MR) is implementation dependent, but VR(MR) should not be set to a value < VR(H). An example of how VR)MR) may be determined is included in Appendix IV of Recommendation Q.2110. */ $Comment /* */ $End_TS_OpDef $Begin_TS_OpDef $TS_OpId APPEND_LIST(parLIST:LIST_TYPE;parLE:INTEGER) $TS_OpResult LIST_TYPE $TS_OpDescription /* This operation is used to append new element of value "parLE" to existing list "parLIST". The procedures of this operation is as follows: 1. Make a instance of LIST_ELEMENT_TYPE which has "00"O as PAD field and bitstring of encoded value of "parLE" as LE field. 2. Append the instance of above to existing list of "parLIST". 3. Return the new list. */ $Comment /* */ $End_TS_OpDef $End_TS_OpDefs $TS_ProcDefs $Begin_TS_ProcDef $TS_ProcId CHECK_N_PS(parPA,parN_PS,parPS:INTEGER) $TS_ProcResult BOOLEAN $Comment /* This operation is used to check if the value of parameter "N(PS)" in STAT PDU is valid or not. */ $TS_ProcDescription VAR LV_parPA:INTEGER:parPA; LV_parN_PS:INTEGER:parN_PS; LV_parPS:INTEGER:parPS; LV_returnvalue:BOOLEAN; ENDVAR BEGIN IF (LV_parPA<=LV_parN_PS) THEN IF (LV_parN_PS<=LV_parPS) THEN LV_returnvalue:= TRUE; ELSE LV_returnvalue:= FALSE; ENDIF; ELSE LV_returnvalue:= FALSE; ENDIF; RETURNVALUE LV_returnvalue; END $End_TS_ProcDescription $Comment /* */ $End_TS_ProcDef $Begin_TS_ProcDef $TS_ProcId INC_MOD_8(parIN, amount:INTEGER) $TS_ProcResult INTEGER $Comment /* INC_MOD_8(parIN, amount) is the modulo incremented value of "parIN" in the amount of "amount". The modulus equals 2E8(256). For example: INC_MOD_8(3,4)=7 INC_MOD_8(255,1)=0 */ $TS_ProcDescription VAR LV_parIN:INTEGER:parIN; LV_amount:INTEGER:amount; LV_returnvalue:INTEGER; ENDVAR BEGIN LV_returnvalue:=(LV_parIN + LV_amount) MOD 256; RETURNVALUE LV_returnvalue; END $End_TS_ProcDescription $Comment /* */ $End_TS_ProcDef $Begin_TS_ProcDef $TS_ProcId INC_MOD_24(parIN, amount:INTEGER) $TS_ProcResult INTEGER $Comment /* INC_MOD_24(parIN, amount) is the modulo incremented value of "parIN" in the amount of "amount". The modulus equals 2E8(16777216). For example: INC_MOD_24(3,4)=7 INC_MOD_24(16777215,1)=0 */ $TS_ProcDescription VAR LV_parIN:INTEGER:parIN; LV_amount:INTEGER:amount; LV_returnvalue:INTEGER; ENDVAR BEGIN LV_returnvalue:=(LV_parIN + LV_amount) MOD 16777216; RETURNVALUE LV_returnvalue; END $End_TS_ProcDescription $Comment /* */ $End_TS_ProcDef $End_TS_ProcDefs $Begin_TS_ParDcls $TS_ParDcl $TS_ParId Max_CC $TS_ParType INTEGER $PICS_PIXITref /* PICS SP1 */ $Comment /* Maximum Number of transmissions of a BGN, END, ER, or RS PDU(MaxCC) */ $End_TS_ParDcl $TS_ParDcl $TS_ParId Max_PD $TS_ParType INTEGER $PICS_PIXITref /* PICS SP2 */ $Comment /* Maximum Number of SD PDUs before transmission of a POLL PDU(MaxPD) */ $End_TS_ParDcl $TS_ParDcl $TS_ParId Max_STAT $TS_ParType INTEGER $PICS_PIXITref /* PICS SP3 */ $Comment /* Maximum Number of list elements placed in a STAT PDU */ $End_TS_ParDcl $TS_ParDcl $TS_ParId TimerPOLLtime $TS_ParType INTEGER $PICS_PIXITref /* PICS SP5 */ $Comment /* The time between transmission of POLL PDU at active phase */ $End_TS_ParDcl $TS_ParDcl $TS_ParId TimerKEEP_ALIVEtime $TS_ParType INTEGER $PICS_PIXITref /* PICS SP6 */ $Comment /* The time between transmission of POLL PDU at transient phase */ $End_TS_ParDcl $TS_ParDcl $TS_ParId TimerNO_RESPONSEtime $TS_ParType INTEGER $PICS_PIXITref /* PICS SP7 */ $Comment /* The maximum time interval during which at least one STAT PDU needs to be received. */ $End_TS_ParDcl $TS_ParDcl $TS_ParId TimerIDLEtime $TS_ParType INTEGER $PICS_PIXITref /* PICS SP8 */ $Comment /* may be considerably greater than Timer_KEEP_ALIVE */ $End_TS_ParDcl $TS_ParDcl $TS_ParId TimerCCtime $TS_ParType INTEGER $PICS_PIXITref /* PICS SP9 */ $Comment /* The time between transmission of BGN, END, ER, or RS PDU */ $End_TS_ParDcl $TS_ParDcl $TS_ParId Power_up_robust $TS_ParType BOOLEAN $PICS_PIXITref /* PIXIT PU1 */ $Comment /* True if the IUT has power-up robustness implemented */ $End_TS_ParDcl $TS_ParDcl $TS_ParId WAITtime $TS_ParType INTEGER $PICS_PIXITref /* PIXIT T1 */ $Comment /* Used to limit the test time waiting for "no response" from the IUT */ $End_TS_ParDcl $TS_ParDcl $TS_ParId TESTtime $TS_ParType INTEGER $PICS_PIXITref /* PIXIT T2 */ $Comment /* The value for the timer that is long enough to allow test operator intervention */ $End_TS_ParDcl $TS_ParDcl $TS_ParId UU_Max_Len $TS_ParType INTEGER $PICS_PIXITref /* PICS SP10 */ $Comment /* PICS SP10 - Maximum length of variable length SSCOP-UU field */ $End_TS_ParDcl $TS_ParDcl $TS_ParId Info_Max_Len $TS_ParType INTEGER $PICS_PIXITref /* PICS SP4 */ $Comment /* PICS SP4 - The maximum length of information field in SD, UD, MD PDUs. This value may be derived from the maximum langth PDU size. (Info_Max_Len = PICS SP4 - 4) */ $End_TS_ParDcl $TS_ParDcl $TS_ParId ST1_BGN $TS_ParType BOOLEAN $PICS_PIXITref /* PIXIT G1 */ $Comment /* Can the IUT send a BGN-PDU on request in state 1? */ $End_TS_ParDcl $TS_ParDcl $TS_ParId ST4_BGN $TS_ParType BOOLEAN $PICS_PIXITref /* PIXIT G2 */ $Comment /* Can the IUT send a BGN-PDU on request at state 4? */ $End_TS_ParDcl $TS_ParDcl $TS_ParId ST2_END $TS_ParType BOOLEAN $PICS_PIXITref /* PIXIT G3 */ $Comment /* Can the IUT send an END-PDU on request at state 2? */ $End_TS_ParDcl $TS_ParDcl $TS_ParId ST5_END $TS_ParType BOOLEAN $PICS_PIXITref /* PIXIT G4 */ $Comment /* Can the IUT send an END-PDU on request at state 5? */ $End_TS_ParDcl $TS_ParDcl $TS_ParId ST10_END $TS_ParType BOOLEAN $PICS_PIXITref /* PIXIT G5 */ $Comment /* Can the IUT send an END-PDU on request at state 10? */ $End_TS_ParDcl $TS_ParDcl $TS_ParId ST10_RS $TS_ParType BOOLEAN $PICS_PIXITref /* PIXIT G6 */ $Comment /* Can the IUT send a RS-PDU on request at state 10? */ $End_TS_ParDcl $TS_ParDcl $TS_ParId ST10_POLL $TS_ParType BOOLEAN $PICS_PIXITref /* PIXIT G7 */ $Comment /* Can the IUT send a POLL-PDU on request at state 10? */ $End_TS_ParDcl $TS_ParDcl $TS_ParId ST10_SD $TS_ParType BOOLEAN $PICS_PIXITref /* PIXIT G8 */ $Comment /* Can the IUT send a SD-PDU on request at state 10? */ $End_TS_ParDcl $Comment /* */ $End_TS_ParDcls $Begin_SelectExprDefs $SelectExprDef $SelectExprId State1_BGN $SelectExpr ST1_BGN $Comment /* Can the IUT send a BGN-PDU on request at state 1? */ $End_SelectExprDef $SelectExprDef $SelectExprId State4_BGN $SelectExpr ST4_BGN $Comment /* Can the IUT send a BGN-PDU on request at state 4? */ $End_SelectExprDef $SelectExprDef $SelectExprId State2_END $SelectExpr ST2_END $Comment /* Can the IUT send an END-PDU on request at state 2? */ $End_SelectExprDef $SelectExprDef $SelectExprId State5_END $SelectExpr ST5_END $Comment /* Can the IUT send an END-PDU on request at state 5? */ $End_SelectExprDef $SelectExprDef $SelectExprId State10_END $SelectExpr ST10_END $Comment /* Can the IUT send an END-PDU on request at state 10? */ $End_SelectExprDef $SelectExprDef $SelectExprId State10_RS $SelectExpr ST10_RS $Comment /* Can the IUT send a RS-PDU on request at state 10? */ $End_SelectExprDef $SelectExprDef $SelectExprId State10_POLL $SelectExpr ST10_POLL $Comment /* Can the IUT send a POLL-PDU on request at state 10? */ $End_SelectExprDef $SelectExprDef $SelectExprId State10_SD $SelectExpr ST10_SD $Comment /* Can the IUT send a SD-PDU on request at state 10? */ $End_SelectExprDef $SelectExprDef $SelectExprId State10_S_P $SelectExpr ST10_SD OR ST10_POLL $Comment /* Can the IUT send a SD-PDU and a POLL-PDU on request at state 10? */ $End_SelectExprDef $Comment /* */ $End_SelectExprDefs $Begin_TS_VarDcls $TS_VarDcl $TS_VarId VT_SQ $TS_VarType INTEGER $TS_VarValue 0 $Comment /* Transmitter Connection Sequence state variable */ $End_TS_VarDcl $TS_VarDcl $TS_VarId VR_SQ $TS_VarType INTEGER $TS_VarValue 0 $Comment /* Receiver Connection Sequence state variable */ $End_TS_VarDcl $Comment /* */ $End_TS_VarDcls $Begin_TC_VarDcls $TC_VarDcl $TC_VarId VT_MS $TC_VarType INTEGER $TC_VarValue 0 $Comment /* Maximum Send state variable */ $End_TC_VarDcl $TC_VarDcl $TC_VarId VR_MR $TC_VarType INTEGER $TC_VarValue $Comment /* Maximum Receive state variable */ $End_TC_VarDcl $TC_VarDcl $TC_VarId VT_S $TC_VarType INTEGER $TC_VarValue 0 $Comment /* Send state variable */ $End_TC_VarDcl $TC_VarDcl $TC_VarId VT_PS $TC_VarType INTEGER $TC_VarValue 0 $Comment /* Poll Send state variable */ $End_TC_VarDcl $TC_VarDcl $TC_VarId VT_A $TC_VarType INTEGER $TC_VarValue 0 $Comment /* Acknowledge state variable */ $End_TC_VarDcl $TC_VarDcl $TC_VarId VT_PA $TC_VarType INTEGER $TC_VarValue 0 $Comment /* Poll Acknowledge state variable */ $End_TC_VarDcl $TC_VarDcl $TC_VarId VT_PD $TC_VarType INTEGER $TC_VarValue 0 $Comment /* Poll Data state variable */ $End_TC_VarDcl $TC_VarDcl $TC_VarId VR_R $TC_VarType INTEGER $TC_VarValue 0 $Comment /* Receive state variable */ $End_TC_VarDcl $TC_VarDcl $TC_VarId VR_H $TC_VarType INTEGER $TC_VarValue 0 $Comment /* Highest expected state variable */ $End_TC_VarDcl $TC_VarDcl $TC_VarId count $TC_VarType INTEGER $TC_VarValue 0 $Comment /* general purpose counter */ $End_TC_VarDcl $TC_VarDcl $TC_VarId TCV_OCT $TC_VarType HEXSTRING $TC_VarValue $Comment /* general purpose */ $End_TC_VarDcl $TC_VarDcl $TC_VarId TCV_N_SQ $TC_VarType INTEGER $TC_VarValue 0 $Comment /* to handle N(SQ) */ $End_TC_VarDcl $TC_VarDcl $TC_VarId TCV_N_MR $TC_VarType INTEGER $TC_VarValue 0 $Comment /* to handle N(MR) */ $End_TC_VarDcl $TC_VarDcl $TC_VarId TCV_N_PS $TC_VarType INTEGER $TC_VarValue 0 $Comment /* to handle N(PS) */ $End_TC_VarDcl $TC_VarDcl $TC_VarId TCV_LIST $TC_VarType LIST_TYPE $TC_VarValue {} $Comment /* to handle LIST field of STAT PDU */ $End_TC_VarDcl $TC_VarDcl $TC_VarId TCV_LIST1 $TC_VarType LIST_TYPE $TC_VarValue {} $Comment /* to handle LIST field of STAT PDU */ $End_TC_VarDcl $Comment /* */ $End_TC_VarDcls $Begin_PCO_TypeDcls $PCO_TypeDcl $PCO_TypeId L_SSCOP $PCO_Role LT $End_PCO_TypeDcl $Comment /* */ $End_PCO_TypeDcls $Begin_PCO_Dcls $PCO_Dcl $PCO_Id LT_PCO $PCO_TypeId L_SSCOP $PCO_Role LT $Comment /* Lower boundary of SSCOP */ $End_PCO_Dcl $Comment /* */ $End_PCO_Dcls $Begin_TimerDcls $TimerDcl $TimerId T_Opr $Duration TESTtime $Unit s $Comment /* This timer is used to allow test operator intervention */ $End_TimerDcl $TimerDcl $TimerId Timer_CC $Duration TimerCCtime $Unit ms $Comment /* The time between transmission of BGN, END, ER, or RS PDU */ $End_TimerDcl $TimerDcl $TimerId Timer_POLL $Duration TimerPOLLtime $Unit ms $Comment /* The time between transmission of POLL PDU at active phase */ $End_TimerDcl $TimerDcl $TimerId Timer_KEEP_ALIVE $Duration TimerKEEP_ALIVEtime $Unit s $Comment /* The time between transmission of POLL PDU at transient phase */ $End_TimerDcl $TimerDcl $TimerId Timer_IDLE $Duration TimerIDLEtime $Unit s $Comment /* may be considerably greater than Timer_KEEP_ALIVE */ $End_TimerDcl $TimerDcl $TimerId Timer_NO_RESPONSE $Duration TimerNO_RESPONSEtime $Unit s $Comment /* The maximum time interval during which at least one STAT PDU needs to be received. */ $End_TimerDcl $TimerDcl $TimerId T_Wait $Duration WAITtime $Unit ms $Comment /* This timer is used when no response is expected from IUT */ $End_TimerDcl $Comment /* */ $End_TimerDcls $PDU_TypeDefs $TTCN_PDU_TypeDefs $Begin_TTCN_PDU_TypeDef $PDU_Id BGAK $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UU $PDU_FieldType OCTETSTRING[0..UU_Max_Len] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD $PDU_FieldType OCTETSTRING[0..3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id BGN $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UU $PDU_FieldType OCTETSTRING[0..UU_Max_Len] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD $PDU_FieldType OCTETSTRING[0..3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_SQ $PDU_FieldType BITSTRING[8] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id BGREJ $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UU $PDU_FieldType OCTETSTRING[0..UU_Max_Len] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD $PDU_FieldType OCTETSTRING[0..3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id ENDAK $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED3 $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id ENDPDU $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UU $PDU_FieldType OCTETSTRING[0..UU_Max_Len] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD $PDU_FieldType OCTETSTRING[0..3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RR $PDU_FieldType BITSTRING[1] $Comment /* "R" is a reserved word in TTCN. */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId S $PDU_FieldType BITSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id ER $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_SQ $PDU_FieldType BITSTRING[8] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id ERAK $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVBGAK $PCO_Type L_SSCOP $Comment /* Used to generate a BGAK PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UUandPAD $PDU_FieldType HEXSTRING[0..INFINITY] $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVBGN $PCO_Type L_SSCOP $Comment /* Used to generate a BGN PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UUandPAD $PDU_FieldType HEXSTRING[0..INFINITY] $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_SQ $PDU_FieldType BITSTRING[8] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* PAD field can be 6 octets(normally 3 octets). */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVBGREJ $PCO_Type L_SSCOP $Comment /* Used to generate a BGREJ PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UUandPAD $PDU_FieldType HEXSTRING[0..INFINITY] $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVEND $PCO_Type L_SSCOP $Comment /* Used to generate a END PDU of incorrec length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UUandPAD $PDU_FieldType HEXSTRING[0..INFINITY] $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RR $PDU_FieldType BITSTRING[1] $Comment /* "R" is a reserved word in TTCN. */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId S $PDU_FieldType BITSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVENDAK $PCO_Type L_SSCOP $Comment /* Used to generate a ENDAK PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId INVALID $PDU_FieldType OCTETSTRING[0..4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED3 $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVER $PCO_Type L_SSCOP $Comment /* Used to generate a ER PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId INVALID $PDU_FieldType OCTETSTRING[0..4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_SQ $PDU_FieldType BITSTRING[8] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVERAK $PCO_Type L_SSCOP $Comment /* Used to generate a ERAK PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId INVALID $PDU_FieldType OCTETSTRING[0..4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVMD $PCO_Type L_SSCOP $Comment /* Used to generate a MD PDU of incorrect langth */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId InformationandPAD $PDU_FieldType HEXSTRING[0..INFINITY] $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVPOLL $PCO_Type L_SSCOP $Comment /* Used to generate a POLL PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId INVALID $PDU_FieldType OCTETSTRING[0..4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_PS $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_S $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVRS $PCO_Type L_SSCOP $Comment /* Used to generate a RS PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UUandPAD $PDU_FieldType HEXSTRING[0..INFINITY] $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_SQ $PDU_FieldType BITSTRING[8] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVRSAK $PCO_Type L_SSCOP $Comment /* Used to generate a RSAK PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId INVALID $PDU_FieldType OCTETSTRING[0..4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVSD $PCO_Type L_SSCOP $Comment /* Used to generate a SD PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId InformationandPAD $PDU_FieldType HEXSTRING[0..INFINITY] $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_S $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVSTAT $PCO_Type L_SSCOP $Comment /* Used to generate a STAT PDU whcih is not 32-bit aligned */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId INVALID $PDU_FieldType OCTETSTRING[0..4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId LIST $PDU_FieldType HEXSTRING[0..INFINITY] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD1 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_PS $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD2 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_R $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVUD $PCO_Type L_SSCOP $Comment /* Used to generate a UD PDU of incorrect langth */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId InformationandPAD $PDU_FieldType HEXSTRING[0..INFINITY] $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id IVUSTAT $PCO_Type L_SSCOP $Comment /* Used to generate a USTAT PDU of incorrect length */ $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId INVALID $PDU_FieldType OCTETSTRING[0..4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD1 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId LE1 $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD2 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId LE2 $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_R $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id MD $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId Information $PDU_FieldType OCTETSTRING[0..Info_Max_Len] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD $PDU_FieldType OCTETSTRING[0..3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id POLL $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_PS $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_S $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id RS $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId UU $PDU_FieldType OCTETSTRING[0..UU_Max_Len] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD $PDU_FieldType OCTETSTRING[0..3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_SQ $PDU_FieldType BITSTRING[8] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id RSAK $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id SD $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId Information $PDU_FieldType OCTETSTRING[0..Info_Max_Len] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD $PDU_FieldType OCTETSTRING[0..3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_S $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id STAT $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId LIST $PDU_FieldType LIST_TYPE $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD1 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_PS $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD2 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_R $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id UD $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId Information $PDU_FieldType OCTETSTRING[0..Info_Max_Len] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD $PDU_FieldType OCTETSTRING[0..3] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PL $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RSVD $PDU_FieldType BITSTRING[2] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED $PDU_FieldType OCTETSTRING[3] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $Begin_TTCN_PDU_TypeDef $PDU_Id USTAT $PCO_Type L_SSCOP $PDU_FieldDcls $PDU_FieldDcl $PDU_FieldId PAD1 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId LE1 $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PAD2 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId LE2 $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED1 $PDU_FieldType OCTETSTRING[1] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_MR $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId RESERVED2 $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId PDU_Type $PDU_FieldType BITSTRING[4] $End_PDU_FieldDcl $PDU_FieldDcl $PDU_FieldId N_R $PDU_FieldType BITSTRING[24] $End_PDU_FieldDcl $End_PDU_FieldDcls $Comment /* */ $End_TTCN_PDU_TypeDef $End_TTCN_PDU_TypeDefs $End_PDU_TypeDefs $End_DeclarationsPart $ConstraintsPart $PDU_Constraints $TTCN_PDU_Constraints $Begin_TTCN_PDU_Constraint $ConsId BGAK_R_GEN $PDU_Id BGAK $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0010'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGAK_S_GEN(parN_MR:INTEGER) $PDU_Id BGAK $DerivPath $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0010'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGAK_S_INV(parN_MR:INTEGER) $PDU_Id BGAK $DerivPath $Comment /* an invalid BGAK PDU which is not 32-bit aligned */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue '00000000000000000000'O $Comment /* 10 octets, PAD must be 2 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $Comment /* 3 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0010'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGN_R_GEN(parN_SQ:INTEGER) $PDU_Id BGN $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue COMPLEMENT(INT_TO_BIT(parN_SQ,8)) $Comment /* retransmitted BGN PDU check */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0001'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGN_R_RET(parN_SQ,parN_MR:INTEGER) $PDU_Id BGN $DerivPath $Comment /* constraint for retransmitted BGN PDU */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0001'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGN_S_CODE(parN_SQ,parN_MR:INTEGER) $PDU_Id BGN $DerivPath $Comment /* an invalid PDU which has an unknown PDU type code */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGN_S_GEN(parN_SQ,parN_MR:INTEGER) $PDU_Id BGN $DerivPath $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0001'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGN_S_INV(parN_SQ,parN_MR:INTEGER) $PDU_Id BGN $DerivPath $Comment /* an invalid BGN PDU which is not 32-bit aligned */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue '00000000000000000000'O $Comment /* 10 octets, PAD must be 2 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $Comment /* 3 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0001'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGREJ_R_GEN $PDU_Id BGREJ $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0111'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGREJ_S_GEN $PDU_Id BGREJ $DerivPath $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0111'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId BGREJ_S_INV $PDU_Id BGREJ $DerivPath $Comment /* an invali BGREJ PDU which is not 32-bit aligned */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue '00000000000000000000'O $Comment /* 10 octets, PAD must be 2 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $Comment /* 3 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0111'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId ENDAK_R_GEN $PDU_Id ENDAK $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0100'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED3 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId ENDAK_S_GEN $PDU_Id ENDAK $DerivPath $Comment /* Constraint for normal SEND */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0100'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED3 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId END_R_GEN $PDU_Id ENDPDU $DerivPath $Comment /* general RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RR $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId S $ConsValue ? $Comment /* IUT resend the last END PDU sent */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId END_R_SSCOP $PDU_Id ENDPDU $DerivPath $Comment /* RECEIVE constraint for SSCOP initiated release */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RR $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId S $ConsValue '1'B $Comment /* SSCOP initiated release */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId END_R_USER $PDU_Id ENDPDU $DerivPath $Comment /* RECEIVE constraint for USER initiated release */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RR $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId S $ConsValue '0'B $Comment /* user initiated release */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId END_S_INV $PDU_Id ENDPDU $DerivPath $Comment /* an invalid END PDU which is not 32-bit aligned */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue '00000000000000000000'O $Comment /* 10 octets, PAD must be 2 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $Comment /* 3 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RR $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId S $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId END_S_SSCOP $PDU_Id ENDPDU $DerivPath $Comment /* SEND constraint for SSCOP initiated release */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RR $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId S $ConsValue '1'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId END_S_USER $PDU_Id ENDPDU $DerivPath $Comment /* SEND constraint for USER initiated release */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RR $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId S $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId ERAK_R_GEN $PDU_Id ERAK $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1111'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId ERAK_S_GEN(parN_MR:INTEGER) $PDU_Id ERAK $DerivPath $Comment /* Constraint for normal SEND */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1111'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId ER_R_GEN(parN_SQ:INTEGER) $PDU_Id ER $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue COMPLEMENT(INT_TO_BIT(parN_SQ,8)) $Comment /* retransmitted ER PDU check */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1001'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId ER_R_RET(parN_SQ,parN_MR:INTEGER) $PDU_Id ER $DerivPath $Comment /* constraint for retransmitted RS PDU */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1001'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId ER_S_GEN(parN_SQ,parN_MR:INTEGER) $PDU_Id ER $DerivPath $Comment /* Constraint fro normal SEND */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1001'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVBGAK_S_INV(parUUandPAD:HEXSTRING;parN_MR:INTEGER) $PDU_Id IVBGAK $DerivPath $Comment /* Used to generate a BGN PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UUandPAD $ConsValue parUUandPAD $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0010'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVBGN_S_INV(parUUandPAD:HEXSTRING;parN_SQ,parN_MR:INTEGER) $PDU_Id IVBGN $DerivPath $Comment /* Used to generate a BGN PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UUandPAD $ConsValue parUUandPAD $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0001'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVBGREJ_S_INV(parUUandPAD:HEXSTRING) $PDU_Id IVBGREJ $DerivPath $Comment /* Used to generate a BGREJ PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UUandPAD $ConsValue parUUandPAD $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0111'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVENDAK_S_INV(parINVALID:OCTETSTRING) $PDU_Id IVENDAK $DerivPath $Comment /* an ENDAK PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId INVALID $ConsValue parINVALID $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0100'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED3 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVEND_S_INV(parUUandPAD:HEXSTRING) $PDU_Id IVEND $DerivPath $Comment /* Used to generate a END PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UUandPAD $ConsValue parUUandPAD $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RR $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId S $ConsValue '0'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVERAK_S_INV(parINVALID:OCTETSTRING;parN_MR:INTEGER) $PDU_Id IVERAK $DerivPath $Comment /* an ERAK PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId INVALID $ConsValue parINVALID $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1111'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVER_S_INV(parINVALID:OCTETSTRING;parN_SQ,parN_MR:INTEGER) $PDU_Id IVER $DerivPath $Comment /* an ER PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId INVALID $ConsValue parINVALID $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1001'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVMD_S_INV(parInformationandPAD:HEXSTRING) $PDU_Id IVMD $DerivPath $Comment /* Used to generate a MD PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId InformationandPAD $ConsValue parInformationandPAD $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1110'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVPOLL_S_INV(parINVALID:OCTETSTRING;parN_PS,parN_S:INTEGER) $PDU_Id IVPOLL $DerivPath $Comment /* Constraint for SEND */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId INVALID $ConsValue parINVALID $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_PS $ConsValue INT_TO_BIT(parN_PS,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1010'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_S $ConsValue INT_TO_BIT(parN_S,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVRSAK_S_INV(parINVALID:OCTETSTRING;parN_MR:INTEGER) $PDU_Id IVRSAK $DerivPath $Comment /* an RSAK PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId INVALID $ConsValue parINVALID $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0110'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVRS_S_INV(parUUandPAD:HEXSTRING;parN_SQ,parN_MR:INTEGER) $PDU_Id IVRS $DerivPath $Comment /* Used to generate a END PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UUandPAD $ConsValue parUUandPAD $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0101'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVSD_S_INV(parInformationandPAD:HEXSTRING;parN_S:INTEGER) $PDU_Id IVSD $DerivPath $Comment /* Used to generate a SD PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId InformationandPAD $ConsValue parInformationandPAD $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_S $ConsValue INT_TO_BIT(parN_S,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVSTAT_S_INV(parLIST:HEXSTRING;parINVALID:OCTETSTRING;parN_PS,parN_MR,parN_R:INTEGER) $PDU_Id IVSTAT $DerivPath $Comment /* an STAT PDU which is not 32-bit aligned */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId INVALID $ConsValue parINVALID $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId LIST $ConsValue parLIST $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_PS $ConsValue INT_TO_BIT(parN_PS,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD2 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR, 24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_R $ConsValue INT_TO_BIT(parN_R, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVUD_S_INV(parInformationandPAD:HEXSTRING) $PDU_Id IVUD $DerivPath $Comment /* Used to generate a UD PDU of incorrect length */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId InformationandPAD $ConsValue parInformationandPAD $Comment /* to generate a PDU of incorrect length */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1101'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId IVUSTAT_S_INV(parLE1,parLE2:INTEGER; parINVALID:OCTETSTRING;parN_MR,parN_R:INTEGER) $PDU_Id IVUSTAT $DerivPath $Comment /* Constraint for SEND with elements variation. */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId INVALID $ConsValue parINVALID $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId LE1 $ConsValue INT_TO_BIT(parLE1,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD2 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId LE2 $ConsValue INT_TO_BIT(parLE2,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1100'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_R $ConsValue INT_TO_BIT(parN_R, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId MD_R_GEN $PDU_Id MD $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1110'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId MD_S_GEN $PDU_Id MD $DerivPath $Comment /* Constraint for normal SEND */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue '0000000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1110'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId MD_S_INV $PDU_Id MD $DerivPath $Comment /* an invalid MD PDU which is not 32-bit aligned */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue '00000000000000000000'O $Comment /* 10 octets, PAD must be 2 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $Comment /* 3 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1110'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId POLL_R_GEN $PDU_Id POLL $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_PS $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1010'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_S $ConsValue ? $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId POLL_S_GEN(parN_PS,parN_S:INTEGER) $PDU_Id POLL $DerivPath $Comment /* Constraint for SEND */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_PS $ConsValue INT_TO_BIT(parN_PS,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1010'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_S $ConsValue INT_TO_BIT(parN_S,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId POLL_S_N_S(parN_PS,parN_S:INTEGER) $PDU_Id POLL $DerivPath $Comment /* Constraint for SEND with N_S variation */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_PS $ConsValue INT_TO_BIT(parN_PS,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1010'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_S $ConsValue INT_TO_BIT(parN_S,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId RSAK_R_GEN $PDU_Id RSAK $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0110'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId RSAK_S_GEN(parN_MR:INTEGER) $PDU_Id RSAK $DerivPath $Comment /* Constraint for normal SEND */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0110'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId RS_R_GEN(parN_SQ:INTEGER) $PDU_Id RS $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue COMPLEMENT(INT_TO_BIT(parN_SQ,8)) $Comment /* retransmitted RS PDU check */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0101'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId RS_R_RET(parN_SQ,parN_MR:INTEGER) $PDU_Id RS $DerivPath $Comment /* constraint for retransmitted RS PDU */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0101'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId RS_S_GEN(parN_SQ,parN_MR:INTEGER) $PDU_Id RS $DerivPath $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0101'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId RS_S_INV(parN_SQ,parN_MR:INTEGER) $PDU_Id RS $DerivPath $Comment /* an invalid RS PDU which is not 32-bit aligned */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId UU $ConsValue '00000000000000000000'O $Comment /* 10 octets, PAD must be 2 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $Comment /* 3 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_SQ $ConsValue INT_TO_BIT(parN_SQ,8) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '0101'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId SD_R_GEN(parN_S:INTEGER) $PDU_Id SD $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_S $ConsValue INT_TO_BIT(parN_S, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId SD_S_GEN(parN_S:INTEGER) $PDU_Id SD $DerivPath $Comment /* Constraint for normal SEND */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue '0000000000'O $Comment /* Must be acceptable by IUT's upper layers */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_S $ConsValue INT_TO_BIT(parN_S,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId SD_S_INV(parN_S:INTEGER) $PDU_Id SD $DerivPath $Comment /* an invalid SD PDU which is not 32-bit aligned */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue '00000000000000000000'O $Comment /* 10 octets, PAD must be 2 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $Comment /* 3 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_S $ConsValue INT_TO_BIT(parN_S,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId SD_S_N_S(parN_S:INTEGER) $PDU_Id SD $DerivPath $Comment /* Constraint for SEND with N_S variation */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue '0000000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_S $ConsValue INT_TO_BIT(parN_S,24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId STAT_R_LIST(parLIST:LIST_TYPE; parN_R:INTEGER) $PDU_Id STAT $DerivPath $Comment /* Constraint for RECEIVE with elements */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId LIST $ConsValue parLIST $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_PS $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD2 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_R $ConsValue INT_TO_BIT(parN_R, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId STAT_R_N_R(parN_R:INTEGER) $PDU_Id STAT $DerivPath $Comment /* Constraint for RECEIVE without element */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId LIST $ConsValue - $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_PS $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD2 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_R $ConsValue INT_TO_BIT(parN_R, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId STAT_R_N_R_S10_Verify(parN_PS:INTEGER) $PDU_Id STAT $DerivPath $Comment /* Constraint for RECEIVE without element */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId LIST $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_PS $ConsValue INT_TO_BIT(parN_PS,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD2 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_R $ConsValue ? $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId STAT_S_N_PS_N_R(parLIST:LIST_TYPE; parN_PS,parN_MR,parN_R:INTEGER) $PDU_Id STAT $DerivPath $Comment /* Constraint for SEND with N_PS and N_R variations. */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId LIST $ConsValue parLIST $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_PS $ConsValue INT_TO_BIT(parN_PS,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD2 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR, 24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1011'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_R $ConsValue INT_TO_BIT(parN_R, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId UD_R_GEN $PDU_Id UD $DerivPath $Comment /* General RECEIVE constraint */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue * $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1101'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId UD_S_GEN $PDU_Id UD $DerivPath $Comment /* Constraint for normal SEND */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue '0000000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1101'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId UD_S_INV $PDU_Id UD $DerivPath $Comment /* an invalid UD PDU which is not 32-bit aligned */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId Information $ConsValue '00000000000000000000'O $Comment /* 10 octets, PAD must be 2 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD $ConsValue '000000'O $Comment /* 3 octets */ $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PL $ConsValue '11'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RSVD $ConsValue '00'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1101'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED $ConsValue '000000'O $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId USTAT_R_LIST(parLE1,parLE2:INTEGER; parN_R:INTEGER) $PDU_Id USTAT $DerivPath $Comment /* Constraint for RECEIVE with LE variation */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId PAD1 $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId LE1 $ConsValue INT_TO_BIT(parLE1, 24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD2 $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId LE2 $ConsValue INT_TO_BIT(parLE2, 24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue ? $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1100'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_R $ConsValue INT_TO_BIT(parN_R, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $Begin_TTCN_PDU_Constraint $ConsId USTAT_S_LIST(parLE1,parLE2:INTEGER; parN_MR,parN_R:INTEGER) $PDU_Id USTAT $DerivPath $Comment /* Constraint for SEND with elements variation. */ $PDU_FieldValues $PDU_FieldValue $PDU_FieldId PAD1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId LE1 $ConsValue INT_TO_BIT(parLE1,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PAD2 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId LE2 $ConsValue INT_TO_BIT(parLE2,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED1 $ConsValue '00'O $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_MR $ConsValue INT_TO_BIT(parN_MR,24) $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId RESERVED2 $ConsValue '0000'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId PDU_Type $ConsValue '1100'B $End_PDU_FieldValue $PDU_FieldValue $PDU_FieldId N_R $ConsValue INT_TO_BIT(parN_R, 24) $End_PDU_FieldValue $End_PDU_FieldValues $Comment /* */ $End_TTCN_PDU_Constraint $End_TTCN_PDU_Constraints $End_PDU_Constraints $End_ConstraintsPart $DynamicPart $TestCases $TestGroup $TestGroupId PC $SelectExprId $Objective /* Protocol Capabilities */ $TestGroup $TestGroupId STATE_1 $SelectExprId $Objective /* */ $TestGroup $TestGroupId VAL $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S1_V_A1 $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestPurpose /* Verify that the IUT generates the BGN PDU on demand at state 1. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(5 of 51)/PICS PC11 */ $SelectExprId State1_BGN $Description /* Verify that the IUT generates the BGN PDU on demand at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref BGN_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?BGN(VR_SQ:=BIT_TO_INT(BGN.N_SQ), VT_MS:=BIT_TO_INT(BGN.N_MR)) CANCEL T_Opr $Cref BGN_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $Comment /* return the IUT in STATE 1 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_V_P1 $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestPurpose /* Verify that the IUT goes to state 3, if power-up robustness is implemented, or sends a BGREJ PDU, if not , on reception of retransmitted BGN PDU. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(5 of 51)/PICS PC12 and Ref X, Fig. 5.1 */ $SelectExprId $Description /* Verify that the IUT goes to state 3, if power-up robustness is implemented, or sends a BGREJ PDU, if not , on reception of retransmitted BGN PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] [Power_up_robust] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId (P) $Comment /* assume a AA-ESTABLISH.response from SSCF UNI */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] [NOT(Power_up_robust)] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [5] LT_PCO?BGREJ CANCEL Timer_CC $Cref BGREJ_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_V_P2 $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestPurpose /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 1. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(5 and 11 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId (P) $Comment /* assume a AA-ESTABLISH.response from SSCF UNI */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGREJ CANCEL Timer_CC $Cref BGREJ_R_GEN $VerdictId (P) $Comment /* (s1) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_V_P5 $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestPurpose /* Verify that the IUT sends a ENDAK PDU on reception of a END PDU at state 1. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(5 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT sends a ENDAK PDU on reception of a END PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDAK CANCEL Timer_CC $Cref ENDAK_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_V_P6 $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestPurpose /* Verify that the IUT ignores a ENDAK PDU and remains at state 1. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(5 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a ENDAK PDU and remains at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDAK $Cref ENDAK_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_V_P16 $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestPurpose /* Verify that the IUT accepts a UD PDU at state 1. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.2 */ $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_V_P17 $TestGroupRef af_test_0067_001/PC/STATE_1/VAL/ $TestPurpose /* Verify that the IUT accepts a MD PDU at state 1. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.3 */ $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INV $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S1_IV_I1 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I2 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_INV(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I3 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I4 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I6 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!RS $Cref RS_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I10 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_INV(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I14 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I15 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I16 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGN $Cref IVBGN_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I17 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGAK $Cref IVBGAK_S_INV(TCV_OCT,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I18 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVBGREJ $Cref IVBGREJ_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I19 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVEND $Cref IVEND_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I20_1 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('00000000'O) $VerdictId $Comment /* extra 4 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I20_2 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('0000'O) $VerdictId $Comment /* extra 2 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I21 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVRS $Cref IVRS_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I22_1 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I22_2 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I23_1 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('00000000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 4 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I23_2 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('0000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 2 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I24_1 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I24_2 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I25 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSD $Cref IVSD_S_INV(TCV_OCT,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I26_1 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('00000000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 4 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I26_2 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('0000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 2 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I27_1 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5,, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'00000000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I27_2 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5,, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'0000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I28_1 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'00000000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I28_2 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTST PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'0000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I29 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVUD $Cref IVUD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I30 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVMD $Cref IVMD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IV_I31 $TestGroupRef af_test_0067_001/PC/STATE_1/INV/ $TestPurpose /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 1. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_CODE(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INOP $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S1_IO_P3 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT sends a END PDU on reception of a BGAK PDU at state 1. */ $DefaultsRef $Comment /* Fig. 20(6 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a BGAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IO_P4 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT ignores a BGREJ PDU and remains at state 1. */ $DefaultsRef $Comment /* Fig. 20(5 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a BGREJ PDU and remains at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IO_P8 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT sends a END PDU on reception of a RS PDU at state 1. */ $DefaultsRef $Comment /* Fig. 20(7 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a RS PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RS $Cref RS_S_GEN(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ENDPDU CANCEL Timer_CC $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IO_P9 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT sends a END PDU on reception of a RSAK PDU at state 1. */ $DefaultsRef $Comment /* Fig. 20(7 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a RSAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RSAK $Cref RSAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IO_P10 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT sends a END PDU on reception of a ER PDU at state 1. */ $DefaultsRef $Comment /* Fig. 20(5 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a ER PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ER $Cref ER_S_GEN(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ENDPDU CANCEL Timer_CC $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IO_P11 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT sends a END PDU on reception of a ERAK PDU at state 1. */ $DefaultsRef $Comment /* Fig. 20(6 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a ERAK PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ERAK $Cref ERAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IO_P12 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT sends a END PDU on reception of a SD PDU at state 1. */ $DefaultsRef $Comment /* Fig. 20(6 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a SD PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IO_P13 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT sends a END PDU on reception of a POLL PDU at state 1. */ $DefaultsRef $Comment /* Fig. 20(6 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a POLL PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!POLL $Cref POLL_S_GEN(VT_PS,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IO_P14 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT sends a END PDU on reception of a STAT PDU at state 1. */ $DefaultsRef $Comment /* Fig. 20(6 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a STAT PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!STAT $Cref STAT_S_N_PS_N_R(TCV_LIST,TCV_N_PS,VR_MR,VR_R) $VerdictId $Comment /* list_length=0 no POLL PDU for TCV_N_PS */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S1_IO_P15 $TestGroupRef af_test_0067_001/PC/STATE_1/INOP/ $TestPurpose /* Verify that the IUT sends a END PDU on reception of a USTAT PDU at state 1. */ $DefaultsRef $Comment /* Fig. 20(6 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a END PDU on reception of a USTAT PDU at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!USTAT $Cref USTAT_S_LIST(1,3, VR_MR,1) $VerdictId $Comment /* elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $End_TestGroup $TestGroup $TestGroupId STATE_2 $SelectExprId State1_BGN $Objective /* */ $TestGroup $TestGroupId VAL $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S2_V_A3 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT generates the END PDU on demand at state 2. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(9 of 51)/PICS PC8 */ $SelectExprId State2_END $Description /* Verify that the IUT generates the END PDU on demand at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDPDU CANCEL T_Opr $Cref END_R_USER $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P1 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a retransmitted BGN PDU at state 2 */ $DefaultsRef $Comment /* Fig. 20(10 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a retransmitted BGN PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P2 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT sends a BGAK PDU on reception of BGN PDU and goes to state 10. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(10 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT sends a BGAK PDU on reception of BGN PDU and goes to state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P3 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT goes to state 10 on reception of BGAK PDU at state 2. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT goes to state 10 on reception of BGAK PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P4 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 2. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P5 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a END PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a END PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P6 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a ENDAK PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a ENDAK PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDAK $Cref ENDAK_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P8 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a RS PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(10 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a RS PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RS $Cref RS_S_GEN(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P9 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a RSAK PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(10 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a RSAK PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RSAK $Cref RSAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P10 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a ER PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a ER PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ER $Cref ER_S_GEN(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P11 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a ERAK PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a ERAK PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ERAK $Cref ERAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P12 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a SD PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a SD PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P13 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a POLL PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a POLL PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!POLL $Cref POLL_S_GEN(VT_PS,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P14 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a STAT PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a STAT PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!STAT $Cref STAT_S_N_PS_N_R(TCV_LIST,TCV_N_PS,VR_MR,VR_R) $VerdictId $Comment /* list_length=0 no POLL PDU for TCV_N_PS */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P15 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT ignores a USTAT PDU and remains at state 2. */ $DefaultsRef $Comment /* Fig. 20(8 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT ignores a USTAT PDU and remains at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!USTAT $Cref USTAT_S_LIST(1,3,VR_MR,1) $VerdictId $Comment /* elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P16 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT accepts a UD PDU at state 2. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.2 */ $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_V_P17 $TestGroupRef af_test_0067_001/PC/STATE_2/VAL/ $TestPurpose /* Verify that the IUT accepts a MD PDU at state 2. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.3 */ $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INV $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S2_IV_I1 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I2 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_INV(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I3 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I4 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I6 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!RS $Cref RS_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I10 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_INV(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I14 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I15 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I16 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGN $Cref IVBGN_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I17 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGAK $Cref IVBGAK_S_INV(TCV_OCT,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I18 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVBGREJ $Cref IVBGREJ_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I19 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVEND $Cref IVEND_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I20_1 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('00000000'O) $VerdictId $Comment /* extra 4 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I20_2 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('0000'O) $VerdictId $Comment /* extra 2 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I21 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVRS $Cref IVRS_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I22_1 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I22_2 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I23_1 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('00000000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 4 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I23_2 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('0000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 2 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I24_1 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I24_2 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I25 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSD $Cref IVSD_S_INV(TCV_OCT,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I26_1 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('00000000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 4 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I26_2 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('0000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 2 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I27_1 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'00000000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I27_2 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'0000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I28_1 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'00000000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I28_2 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTST PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'0000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I29 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVUD $Cref IVUD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I30 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVMD $Cref IVMD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S2_IV_I31 $TestGroupRef af_test_0067_001/PC/STATE_2/INV/ $TestPurpose /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 2. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_CODE(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $End_TestGroup $TestGroup $TestGroupId STATE_4 $SelectExprId State10_END $Objective /* */ $TestGroup $TestGroupId VAL $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S4_V_A1 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT generates the BGN PDU on demand at state 4. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(14 of 51)/PICS PC11 */ $SelectExprId State4_BGN $Description /* Verify that the IUT generates the BGN PDU on demand at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref BGN_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?BGN(VR_SQ:=BIT_TO_INT(BGN.N_SQ), VT_MS:=BIT_TO_INT(BGN.N_MR)) CANCEL T_Opr $Cref BGN_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S2_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P1 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT sends a BGAK and END PDU on reception of retransmitted BGN PDU at state 4. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(16 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a BGAK and END PDU on reception of retransmitted BGN PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [6] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_USER $VerdictId (P) $Comment /* resend the last END PDU sent */ $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P2 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 4. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(16 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ) (s3) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId (P) $Comment /* (s10) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGREJ CANCEL Timer_CC $Cref BGREJ_R_GEN $VerdictId (P) $Comment /* (s1) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P3 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT ignores a BGAK PDU and remains at state 4. */ $DefaultsRef $Comment /* Fig. 20(14 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a BGAK PDU and remains at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P4 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 4. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(15 of 51) */ $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P5 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT sends a ENDAK PDU on reception of a END PDU at state 4. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(15 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT sends a ENDAK PDU on reception of a END PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDAK CANCEL Timer_CC $Cref ENDAK_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P6 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT goes to state 1 on reception of ENDAK PDU at state 4. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(15 of 51) */ $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of ENDAK PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDAK $Cref ENDAK_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P8 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT ignores a RS PDU and remains at state 4. */ $DefaultsRef $Comment /* Fig. 20(16 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a RS PDU and remains at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RS $Cref RS_S_GEN(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] (VT_SQ:=VT_SQ-1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P9 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT ignores a RSAK PDU and remains at state 4. */ $DefaultsRef $Comment /* Fig. 20(16 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a RSAK PDU and remains at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RSAK $Cref RSAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P10 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT ignores a ER PDU and remains at state 4. */ $DefaultsRef $Comment /* Fig. 20(16 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a ER PDU and remains at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ER $Cref ER_S_GEN(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] (VT_SQ:=VT_SQ-1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P11 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT ignores a ERAK PDU and remains at state 4. */ $DefaultsRef $Comment /* Fig. 20(15 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a ERAK PDU and remains at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ERAK $Cref ERAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P12 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT ignores a SD PDU and remains at state 4. */ $DefaultsRef $Comment /* Fig. 20(14 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a SD PDU and remains at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P13 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT ignores a POLL PDU and remains at state 4. */ $DefaultsRef $Comment /* Fig. 20(14 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a POLL PDU and remains at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!POLL $Cref POLL_S_GEN(VT_PS,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P14 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT ignores a STAT PDU and remains at state 4. */ $DefaultsRef $Comment /* Fig. 20(14 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a STAT PDU and remains at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!STAT $Cref STAT_S_N_PS_N_R(TCV_LIST,TCV_N_PS,VR_MR,VR_R) $VerdictId $Comment /* list_length=0 no POLL PDU for TCV_N_PS */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P15 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT ignores a USTAT PDU and remains at state 4. */ $DefaultsRef $Comment /* Fig. 20(14 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a USTAT PDU and remains at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!USTAT $Cref USTAT_S_LIST(1,3,VR_MR,1) $VerdictId $Comment /* elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P16 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT accepts a UD PDU at state 4. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.2 */ $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_V_P17 $TestGroupRef af_test_0067_001/PC/STATE_4/VAL/ $TestPurpose /* Verify that the IUT accepts a MD PDU at state 4. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.3 */ $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INV $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S4_IV_I1 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] (VT_SQ:=VT_SQ-1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I2 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_INV(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I3 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I4 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I6 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!RS $Cref RS_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I10 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_INV(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I14 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I15 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I16 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGN $Cref IVBGN_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] (VT_SQ:=VT_SQ-1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I17 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGAK $Cref IVBGAK_S_INV(TCV_OCT,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I18 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVBGREJ $Cref IVBGREJ_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I19 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVEND $Cref IVEND_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I20_1 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('00000000'O) $VerdictId $Comment /* extra 4 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I20_2 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('0000'O) $VerdictId $Comment /* extra 2 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I21 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVRS $Cref IVRS_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I22_1 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I22_2 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I23_1 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('00000000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 4 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I23_2 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('0000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 2 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I24_1 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I24_2 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I25 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSD $Cref IVSD_S_INV(TCV_OCT,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I26_1 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('00000000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 4 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I26_2 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('0000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 2 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I27_1 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'00000000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I27_2 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'0000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I28_1 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'00000000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I28_2 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTST PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'0000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I29 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVUD $Cref IVUD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I30 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVMD $Cref IVMD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_IV_I31 $TestGroupRef af_test_0067_001/PC/STATE_4/INV/ $TestPurpose /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 4. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_CODE(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $End_TestGroup $TestGroup $TestGroupId STATE_5 $SelectExprId State10_RS $Objective /* */ $TestGroup $TestGroupId VAL $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S5_V_A3 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT generates the END PDU on demand at state 5. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(18 of 51)/PICS PC8 */ $SelectExprId State5_END $Description /* Verify that the IUT generates the END PDU on demand at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDPDU CANCEL T_Opr $Cref END_R_USER $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P1 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT sends a BGAK and RS PDU on reception of retransmitted BGN PDU at state 5 */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(17 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a BGAK and RS PDU on reception of retransmitted BGN PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [6] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ), VT_MS:=BIT_TO_INT(RS.N_MR)) CANCEL T_Wait $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P2 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 5. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(17 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 5 */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ)(s3) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId (P) $Comment /* (s10) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGREJ CANCEL Timer_CC $Cref BGREJ_R_GEN $VerdictId (P) $Comment /* (s1) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P3 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT ignores a BGAK PDU and remains at state 5. */ $DefaultsRef $Comment /* Fig. 20(19 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a BGAK PDU and remains at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P5 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT sends a ENDAK PDU on reception of a END PDU at state 5. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(17 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT sends a ENDAK PDU on reception of a END PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDAK CANCEL Timer_CC $Cref ENDAK_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P7 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT ignores a retransmitted RS PDU and remains at state 5. */ $DefaultsRef $Comment /* Fig. 20(19 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a retransmitted RS PDU and remains at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RS $Cref RS_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P8 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT sends a RSAK PDU on reception of RS PDU and goes to state 10. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(19 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT sends a RSAK PDU on reception of RS PDU and goes to state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RS $Cref RS_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?RSAK(VT_MS:=BIT_TO_INT(RSAK.N_MR)) CANCEL Timer_CC $Cref RSAK_R_GEN $VerdictId (P) $Comment /* assume a AA-RESYNC.response from SSCF UNI */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P9 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT goes to state 10 on reception of RSAK PDU at state 5. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(19 of 51)/PICS PC6 */ $SelectExprId $Description /* Verify that the IUT goes to state 10 on reception of RSAK PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RSAK $Cref RSAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P10 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT ignores a ER PDU and remains at state 5. */ $DefaultsRef $Comment /* Fig. 20(17 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a ER PDU and remains at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ER $Cref ER_S_GEN(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] (VT_SQ:=VT_SQ-1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS $Cref RS_R_RET(VR_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P11 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT ignores a ERAK PDU and remains at state 5. */ $DefaultsRef $Comment /* Fig. 20(19 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a ERAK PDU and remains at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ERAK $Cref ERAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P12 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT ignores a SD PDU and remains at state 5. */ $DefaultsRef $Comment /* Fig. 20(19 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a SD PDU and remains at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P13 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT ignores a POLL PDU and remains at state 5. */ $DefaultsRef $Comment /* Fig. 20(17 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a POLL PDU and remains at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!POLL $Cref POLL_S_GEN(VT_PS,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P14 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT ignores a STAT PDU and remains at state 5. */ $DefaultsRef $Comment /* Fig. 20(18 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a STAT PDU and remains at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!STAT $Cref STAT_S_N_PS_N_R(TCV_LIST,TCV_N_PS,VR_MR,VR_R) $VerdictId $Comment /* list_length=0 no POLL PDU for TCV_N_PS */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P15 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT ignores a USTAT PDU and remains at state 5. */ $DefaultsRef $Comment /* Fig. 20(18 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a USTAT PDU and remains at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!USTAT $Cref USTAT_S_LIST(1,3,VR_MR,1) $VerdictId $Comment /* elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P16 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT accepts a UD PDU at state 5. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.2 */ $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_V_P17 $TestGroupRef af_test_0067_001/PC/STATE_5/VAL/ $TestPurpose /* Verify that the IUT accepts a MD PDU at state 5. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.3 */ $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INV $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S5_IV_I1 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] (VT_SQ:=VT_SQ-1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I2 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_INV(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I3 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I4 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I6 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!RS $Cref RS_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I10 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_INV(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I14 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I15 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I16 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGN $Cref IVBGN_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] (VT_SQ:=VT_SQ-1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I17 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGAK $Cref IVBGAK_S_INV(TCV_OCT,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I18 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVBGREJ $Cref IVBGREJ_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I19 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVEND $Cref IVEND_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I20_1 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('00000000'O) $VerdictId $Comment /* extra 4 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I20_2 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('0000'O) $VerdictId $Comment /* extra 2 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I21 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVRS $Cref IVRS_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I22_1 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I22_2 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I23_1 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('00000000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 4 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I23_2 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('0000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 2 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I24_1 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I24_2 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I25 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSD $Cref IVSD_S_INV(TCV_OCT,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I26_1 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('00000000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 4 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I26_2 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('0000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 2 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I27_1 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'00000000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I27_2 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'0000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I28_1 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'00000000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I28_2 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTST PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'0000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I29 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVUD $Cref IVUD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I30 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVMD $Cref IVMD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IV_I31 $TestGroupRef af_test_0067_001/PC/STATE_5/INV/ $TestPurpose /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 5. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_CODE(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INOP $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S5_IO_P4 $TestGroupRef af_test_0067_001/PC/STATE_5/INOP/ $TestPurpose /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 5. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(17 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_IO_P6 $TestGroupRef af_test_0067_001/PC/STATE_5/INOP/ $TestPurpose /* Verify that the IUT goes to state 1 on reception of ENDAK PDU at state 5. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(17 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of ENDAK PDU at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDAK $Cref ENDAK_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ),VT_MS:=BIT_TO_INT(RS.N_MR)) $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $End_TestGroup $TestGroup $TestGroupId STATE_7 $SelectExprId $Objective /* */ $TestGroup $TestGroupId VAL $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S7_V_P2 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 7. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(25 and 11 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT goes to state 3 on reception of BGN PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ)(s3) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +Initialize_State_Variables $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId (P) $Comment /* assume a AA-ESTABLISH.response from SSCF UNI (s10) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?BGREJ CANCEL Timer_CC $Cref BGREJ_R_GEN $VerdictId (P) $Comment /* (s1) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P5 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT sends a ENDAK PDU and goes to state 1 on reception of a END PDU at state 7. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(23 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT sends a ENDAK PDU and goes to state 1 on reception of a END PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDAK CANCEL Timer_CC $Cref ENDAK_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P8 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT goes to state 6 on reception of RS PDU at state 7. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(26 and 11 of 51) */ $SelectExprId $Description /* Verify that the IUT goes to state 6 on reception of RS PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RS $Cref RS_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +Initialize_State_Variables $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] LT_PCO?RSAK(VT_MS:=BIT_TO_INT(RSAK.N_MR)) CANCEL Timer_CC $Cref RSAK_R_GEN $VerdictId (P) $Comment /* assume a AA-RESYNC.response from SSCF UNI */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P11 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT sends a ERAK PDU and goes to state 8 on reception of a ER PDU at state 7. */ $DefaultsRef $Comment /* Ref. 5.0 i, Fig. 20(25 of 51) */ $SelectExprId $Description /* Verify that the IUT sends a ERAK PDU and goes to state 8 on reception of a ER PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ER $Cref ER_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +Initialize_State_Variables $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] LT_PCO?ERAK(VT_MS:=BIT_TO_INT(ERAK.N_MR)) CANCEL Timer_CC $Cref ERAK_R_GEN $VerdictId (P) $Comment /* assume a AA-RECOVER.response from SSCF UNI */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P12 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT goes to state 8 on reception of ERAK PDU at state 7. */ $DefaultsRef $Comment /* Ref. 5.0 i, Fig. 20(23 of 51) */ $SelectExprId $Description /* Verify that the IUT goes to state 8 on reception of ERAK PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ERAK $Cref ERAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +Initialize_State_Variables $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P19 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT ignores a SD PDU and remains at state 7. */ $DefaultsRef $Comment /* Fig. 20(25 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a SD PDU and remains at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P21 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT ignores a POLL PDU and remains at state 7. */ $DefaultsRef $Comment /* Fig. 20(24 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a POLL PDU and remains at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!POLL $Cref POLL_S_GEN(VT_PS,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P26 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT ignores a STAT PDU and remains at state 7. */ $DefaultsRef $Comment /* Fig. 20(24 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a STAT PDU and remains at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!STAT $Cref STAT_S_N_PS_N_R(TCV_LIST,TCV_N_PS,VR_MR,VR_R) $VerdictId $Comment /* list_length=0 no POLL PDU for TCV_N_PS */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P36 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT ignores a USTAT PDU and remains at state 7. */ $DefaultsRef $Comment /* Fig. 20(24 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a USTAT PDU and remains at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!USTAT $Cref USTAT_S_LIST(1,3,VR_MR,1) $VerdictId $Comment /* elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P40 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT accepts a UD PDU at state 7. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.2 */ $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_V_P41 $TestGroupRef af_test_0067_001/PC/STATE_7/VAL/ $TestPurpose /* Verify that the IUT accepts a MD PDU at state 7. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.3 */ $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INV $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S7_IV_I1 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I2 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_INV(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I3 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I4 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I6 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!RS $Cref RS_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I10 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_INV(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I14 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I15 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I16 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGN $Cref IVBGN_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I17 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGAK $Cref IVBGAK_S_INV(TCV_OCT,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I18 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVBGREJ $Cref IVBGREJ_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I19 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVEND $Cref IVEND_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I20_1 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('00000000'O) $VerdictId $Comment /* extra 4 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I20_2 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('0000'O) $VerdictId $Comment /* extra 2 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I21 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVRS $Cref IVRS_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I22_1 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I22_2 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I23_1 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('00000000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 4 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I23_2 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('0000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 2 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I24_1 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I24_2 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I25 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSD $Cref IVSD_S_INV(TCV_OCT,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I26_1 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('00000000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 4 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I26_2 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('0000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 2 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I27_1 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'00000000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I27_2 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'0000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I28_1 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'00000000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I28_2 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTST PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'0000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I29 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVUD $Cref IVUD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I30 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVMD $Cref IVMD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IV_I31 $TestGroupRef af_test_0067_001/PC/STATE_7/INV/ $TestPurpose /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 7. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_CODE(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INOP $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S7_IO_P1 $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestPurpose /* Verify that the IUT ignores a retransmitted BGN PDU and remains at state 7. */ $DefaultsRef $Comment /* Fig. 20(25 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a retransmitted BGN PDU and remains at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ER $Cref ER_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IO_P3 $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestPurpose /* Verify that the IUT ignores a BGAK PDU and remains at state 7. */ $DefaultsRef $Comment /* Fig. 20(23 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a BGAK PDU and remains at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IO_P4 $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestPurpose /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 7. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(23 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of BGREJ PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IO_P6 $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestPurpose /* Verify that the IUT goes to state 1 on reception of ENDAK PDU at state 7. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(23 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT goes to state 1 on reception of ENDAK PDU at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDAK $Cref ENDAK_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IO_P7 $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestPurpose /* Verify that the IUT ignores a retransmitted RS PDU and remains at state 7. */ $DefaultsRef $Comment /* Fig. 20(19 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a retransmitted RS PDU and remains at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RS $Cref RS_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ER $Cref ER_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IO_P9 $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestPurpose /* Verify that the IUT ignores a RSAK PDU and remains at state 7. */ $DefaultsRef $Comment /* Fig. 20(23 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a RSAK PDU and remains at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RSAK $Cref RSAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_IO_P10 $TestGroupRef af_test_0067_001/PC/STATE_7/INOP/ $TestPurpose /* Verify that the IUT ignores a retransmitted ER PDU and remains at state 7. */ $DefaultsRef $Comment /* Fig. 20(25 of 51) */ $SelectExprId $Description /* Verify that the IUT ignores a retransmitted ER PDU and remains at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ER $Cref ER_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT Timer_CC $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?ER $Cref ER_R_RET(VR_SQ,VT_MS) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $End_TestGroup $TestGroup $TestGroupId STATE_10 $SelectExprId $Objective /* */ $TestGroup $TestGroupId VAL $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S10_V_A3 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, generates the END PDU on demand. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(34 of 51)/PICS PC8 */ $SelectExprId State10_END $Description /* Verify that the IUT, at state 10, generates the END PDU on demand. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDPDU CANCEL T_Opr $Cref END_R_USER $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S4_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $Comment /* return the IUT in STATE 1 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_A5 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, generates the RS PDU on demand. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(34 of 51)/PICS PC6 */ $SelectExprId State10_RS $Description /* Verify that the IUT, at state 10, generates the RS PDU on demand. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref RS_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ), VT_MS:=BIT_TO_INT(RS.N_MR)) CANCEL T_Opr $Cref RS_R_GEN(VR_SQ) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S5_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $Comment /* return the IUT in STATE 1 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P1 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a BGAK PDU on reception of a retransmitted BGN PDU. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(35 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a BGAK PDU on reception of a retransmitted BGN PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P2 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, goes to state 3 on reception of BGN PDU. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(35 and 11 of 51)/PICS PC7 */ $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 3 on reception of BGN PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId (P) $Comment /* assume a AA-ESTABLISH.response from SSCF UNI */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?BGREJ CANCEL Timer_CC $Cref BGREJ_R_GEN $VerdictId (P) $Comment /* (s1) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P3 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, ignores a BGAK PDU and remains. */ $DefaultsRef $Comment /* Fig. 20(34 of 51) */ $SelectExprId $Description /* Verify that the IUT, at state 10, ignores a BGAK PDU and remains. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P5 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a ENDAK PDU and goes to state 1 on reception of a END PDU. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(36 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ENDAK PDU and goes to state 1 on reception of a END PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDAK CANCEL Timer_CC $Cref ENDAK_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P7 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a RSAK PDU on reception of a retransmitted RS PDU. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(36 of 51) */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a RSAK PDU on reception of a retransmitted RS PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RS $Cref RS_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?RSAK(VT_MS:=BIT_TO_INT(RSAK.N_MR)) CANCEL Timer_CC $Cref RSAK_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P8 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, goes to state 6 on reception of RS PDU. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(36 of 51) */ $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 6 on reception of RS PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RS $Cref RS_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?RSAK(VT_MS:=BIT_TO_INT(RSAK.N_MR)) CANCEL Timer_CC $Cref RSAK_R_GEN $VerdictId (P) $Comment /* assume a AA-RESYNC.response from SSCF UNI */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P9 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, ignores a RSAK PDU and remains. */ $DefaultsRef $Comment /* Fig. 20(34 of 51) */ $SelectExprId $Description /* Verify that the IUT, at state 10, ignores a RSAK PDU and remains. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!RSAK $Cref RSAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P10 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a ERAK PDU on reception of a retransmitted ER PDU. */ $DefaultsRef $Comment /* Fig. 20(35 of 51) */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a ERAK PDU on reception of a retransmitted ER PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ER $Cref ER_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)=VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ERAK(VT_MS:=BIT_TO_INT(ERAK.N_MR)) CANCEL Timer_CC $Cref ERAK_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P11 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, goes to state 9 on reception of ER PDU. */ $DefaultsRef $Comment /* Ref. 5.0 i, Fig. 20(35 of 51) */ $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 9 on reception of ER PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ER $Cref ER_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* N(SQ)<>VR(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ERAK(VT_MS:=BIT_TO_INT(ERAK.N_MR)) CANCEL Timer_CC $Cref ERAK_R_GEN $VerdictId (P) $Comment /* assume a AA-RECOVER.response from SSCF UNI */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_CC $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P12 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, ignores a ERAK PDU and remains. */ $DefaultsRef $Comment /* Fig. 20(34 of 51) */ $SelectExprId $Description /* Verify that the IUT, at state 10, ignores a ERAK PDU and remains. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!ERAK $Cref ERAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P13 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a USTAT PDU on reception of SD PDU out of the window. */ $DefaultsRef $Comment /* Ref. 5.0 a, h, Fig. 20(40 of 51)/PICS PC5.1 */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a USTAT PDU on reception of SD PDU out of the window. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $Comment /* VR(R)=VR(H)=1 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!SD $Cref SD_S_N_S(VT_MS+2) $VerdictId $Comment /* SD.N(S)>=VR(MR) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?USTAT(VT_MS:=BIT_TO_INT(USTAT.N_MR)) CANCEL T_Wait $Cref USTAT_R_LIST(VT_S+1, VT_MS, VT_S+1) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] (VT_S:=VT_MS+2+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* SD.N(S)>=VR(MR), VR(H)=VR(MR) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [7] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [8] (VT_S:=VT_MS+2+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* SD.N(S)>=VR(MR), VR(H)>=VR(MR) */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P15 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, saves the next highest expected SD PDU. */ $DefaultsRef $Comment /* Ref. 5.0 a, h, Fig. 20(40 of 51)/PICS PC5.1 */ $SelectExprId $Description /* Verify that the IUT, at state 10, saves the next highest expected SD PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_N_S(VT_S+2) $VerdictId $Comment /* SD.N(S)>VR(H) IUT saves this SD PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?USTAT(VT_MS:=BIT_TO_INT(USTAT.N_MR)) CANCEL T_Wait $Cref USTAT_R_LIST(VT_S, VT_S+2,VT_S) $VerdictId $Comment /* VR(R)=0, VR(H)=3 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO!SD $Cref SD_S_N_S(VT_S+3) $VerdictId $Comment /* SD.N(S)=VR(H) IUT saves this SD PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO!SD $Cref SD_S_N_S(VT_S) $VerdictId $Comment /* IUT indicate PDU(0) VR(R)=1, VR(H)=4 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO!SD $Cref SD_S_N_S(VT_S+1) $VerdictId $Comment /* IUT indicate PDUs(1,2,3) VR(R)=4, VR(H)=4 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [7] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] LT_PCO!POLL $Cref POLL_S_N_S(VT_PS,VT_S+4) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [10] LT_PCO?STAT[CHECK_N_PS(VT_PA,BIT_TO_INT(STAT.N_PS),VT_PS)](VT_MS:=BIT_TO_INT(STAT.N_MR)) CANCEL T_Wait $Cref STAT_R_N_R(VT_S+4) $VerdictId (P) $Comment /* list_length=0 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [11] (VT_S:=5) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* SD.N(S)VR(R),SD.N(S)=VR(H) */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P17 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, saves a SD PDU that sequence number is between the sequence number of the next in sequence and the next highest expected SD PDUs. */ $DefaultsRef $Comment /* Ref. 5.0 a, h, Fig. 20(40 of 51)/PICS PC5.1 */ $SelectExprId $Description /* Verify that the IUT, at state 10, saves a SD PDU that sequence number is between the sequence number of the next in sequence and the next highest expected SD PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_N_S(VT_S+2) $VerdictId $Comment /* SD.N(S)>VR(H) IUT saves this SD PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?USTAT(VT_MS:=BIT_TO_INT(USTAT.N_MR)) CANCEL T_Wait $Cref USTAT_R_LIST(VT_S, VT_S+2,VT_S) $VerdictId $Comment /* VR(R)=0, VR(H)=3 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO!SD $Cref SD_S_N_S(VT_S+1) $VerdictId $Comment /* SD.N(S)VR(R), SD.N(S)VR(H) IUT saves this SD PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?USTAT(VT_MS:=BIT_TO_INT(USTAT.N_MR)) CANCEL T_Wait $Cref USTAT_R_LIST(VT_S, VT_S+2, VT_S) $VerdictId $Comment /* VR(R)=0, VR(H)=3 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO!SD $Cref SD_S_N_S(VT_S+2) $VerdictId $Comment /* SD.N(S)VR(R), SD.N(S)=VR(H),POLL.N(S)>VR(MR),VR(R)=VR(H) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] (TCV_LIST:=APPEND_LIST(TCV_LIST,VT_S), TCV_LIST:=APPEND_LIST(TCV_LIST,VT_MS)) CANCEL T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] LT_PCO?STAT[CHECK_N_PS(VT_PA,BIT_TO_INT(STAT.N_PS),VT_PS)] $Cref STAT_R_LIST(TCV_LIST, VT_S) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] (VT_S:=VT_MS+2+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* POLL.N(S)>=VR(H), POLL.N(S)>VR(MR), VR(R)=VR(H) */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P23_1 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a STAT PDU on reception of a POLL PDU that sequence number is greater than that of the next highest expected SD PDU and is out of the window. */ $DefaultsRef $Comment /* Ref. 5.0 a, h, Fig. 20(41and 42 of 51)/PICS PC5.1 */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a STAT PDU on reception of a POLL PDU that sequence number is greater than that of the next highest expected SD PDU and is out of the window. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $Comment /* send SD(0) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VT_S:=INC_MOD_24(VT_S,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!SD $Cref SD_S_N_S(VT_S+3) $VerdictId $Comment /* send SD(4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] LT_PCO?USTAT CANCEL T_Wait $Cref USTAT_R_LIST(VT_S,VT_S+3,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] (TCV_LIST:=APPEND_LIST(TCV_LIST,VT_S), TCV_LIST:=APPEND_LIST(TCV_LIST,VT_S+3), TCV_LIST:=APPEND_LIST(TCV_LIST,VT_S+4)) $Cref $VerdictId $Comment /* element1=1 element2=4 element3=5 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [7] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] LT_PCO!POLL $Cref POLL_S_N_S(VT_PS,VT_S+4) $VerdictId $Comment /* POLL(5) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [9] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [10] LT_PCO?STAT[CHECK_N_PS(VT_PA,BIT_TO_INT(STAT.N_PS),VT_PS)] CANCEL T_Wait $Cref STAT_R_LIST(TCV_LIST, VT_S) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [11] (VT_S:=VT_S+4+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* POLL.N(S)>=VR(H), POLL.N(S)>VR(MR), VR(R)=Max_STAT] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] (VT_S:=INC_MOD_24(VT_S,2)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $Comment /* send SD(x+2) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [13] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB5 $Line [14] LT_PCO?USTAT CANCEL T_Wait $Cref USTAT_R_LIST(VT_S-1, VT_S, 1) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [15] (TCV_LIST1:=APPEND_LIST(TCV_LIST1,VT_S), TCV_LIST1:=APPEND_LIST(TCV_LIST1,VT_S+1), TCV_LIST1:=APPEND_LIST(TCV_LIST1,VT_S+2)) $Cref $VerdictId $Comment /* LE=X+1 LE=x+2 LE=VT_MS */ $End_BehaviourLine $BehaviourLine $LabelId $Line [16] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [17] LT_PCO!POLL $Cref POLL_S_N_S(VT_PS,VT_S+2) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [18] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [19] LT_PCO?STAT[CHECK_N_PS(VT_PA,BIT_TO_INT(STAT.N_PS),VT_PS)] CANCEL T_Wait $Cref STAT_R_LIST(TCV_LIST, 1) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [20] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB3 $Line [21] LT_PCO?STAT[CHECK_N_PS(VT_PA,BIT_TO_INT(STAT.N_PS),VT_PS)] CANCEL T_Wait $Cref STAT_R_LIST(TCV_LIST1, 1) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [22] +RESTORE_SEQUENCE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [23] (VT_S:=VT_S+2+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [24] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [25] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [21] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [22] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [21] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [22] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [21] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [22] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [21] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [19] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [20] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [19] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [20] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [19] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [20] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [19] LT_PCO?USTAT $Cref USTAT_R_LIST(VT_S-1, VT_S, 1) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [20] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [19] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [15] GOTO LB5 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [15] GOTO LB5 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [15] GOTO LB5 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?OTHERWISE $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] ?TIMEOUT T_Wait $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* POLL.N(S)>=VR(H), POLL.N(S)>VR(MR), VR(R)=VR(H),POLL.N(S),=VR(MR),VR(R)=VR(H) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [7] LT_PCO?STAT[CHECK_N_PS(VT_PA,BIT_TO_INT(STAT.N_PS),VT_PS)] CANCEL T_Wait $Cref STAT_R_N_R(VT_S+3) $VerdictId (P) $Comment /* STAT.LIST=null STAT.N_R=3 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [8] (VT_S:=VT_S+3+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* POLL.N(S)>=VR(H), POLL.N(S)<=VR(MR), VR(R)=VR(H) */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P25 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10 and having a missing gap of received SD PDU, sends a STAT PDU on reception of a POLL PDU that sequence number is less than or equal to that of the next highest expected SD PDU and is within the window. */ $DefaultsRef $Comment /* Ref. 5.0 a, h, Fig. 20(41 and 42 of 51)/PICS PC5.1 */ $SelectExprId $Description /* Verify that the IUT, at state 10 and having a missing gap of received SD PDUs, sends a STAT PDU on reception of a POLL PDU that sequence number is less than or equal to that of the next highest expected SD PDU and is within the window. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $Comment /* send SD(0) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!SD $Cref SD_S_N_S(VT_S+1) $VerdictId $Comment /* send SD(1) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!SD $Cref SD_S_N_S(VT_S+3) $VerdictId $Comment /* send SD(3) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] LT_PCO?USTAT $Cref USTAT_R_LIST(VT_S+2,VT_S+3,VT_S+2) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] CANCEL T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] (TCV_LIST:=APPEND_LIST(TCV_LIST,VT_S+2), TCV_LIST:=APPEND_LIST(TCV_LIST,VT_S+3), TCV_LIST:=APPEND_LIST(TCV_LIST,VT_S+4)) $Cref $VerdictId $Comment /* LE=X+1 LE=x+2 LE=VT_MS */ $End_BehaviourLine $BehaviourLine $LabelId $Line [8] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO!POLL $Cref POLL_S_N_S( VT_PS,VT_S+4) $VerdictId $Comment /* POLL.N(S)>=VR(H),POLL.N(S),=VR(MR),VR(R)=VR(H), POLL.N(S)<=VR(MR), VR(R) $Cref POLL_R_GEN $VerdictId $Comment /* VT(PA)=1 VT(PS)=1 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?POLL(TCV_N_PS:=BIT_TO_INT(POLL.N_PS)) CANCEL T_Opr $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO!STAT $Cref STAT_S_N_PS_N_R(TCV_LIST,TCV_N_PS,VR_MR,3) $VerdictId $Comment /* STAT.N(R)=3 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [7] LT_PCO?ER(VR_SQ:=BIT_TO_INT(ER.N_SQ), VT_MS:=BIT_TO_INT(ER.N_MR)) CANCEL T_Wait $Cref ER_R_GEN(VR_SQ) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* VT(PA)<=STAT.N(PS)<=VT(PS), not(VT(A)<=STAT.N(R)<=VT(S)) */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P32 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a STAT PDU that poll sequence number and SD PDU sequence number are correct but its list element has incorrect sequence number. */ $DefaultsRef $Comment /* Ref. 5.0 i, Fig. 20(44, 45 and 41 of 51)/PICS PC5.1 */ $SelectExprId State10_POLL $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a STAT PDU that poll sequence number and SD PDU sequence number are correct but its list element has incorrect sequence number. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $Comment /* VT(PA)=0 VT(PS)=0 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref POLL_R_GEN $VerdictId $Comment /* VT(PA)=1 VT(PS)=1 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?POLL(TCV_N_PS:=BIT_TO_INT(POLL.N_PS)) CANCEL T_Opr $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] (TCV_LIST:=APPEND_LIST(TCV_LIST,VR_R+2), TCV_LIST:=APPEND_LIST(TCV_LIST,VR_R+3)) $Cref $VerdictId $Comment /* list element has incorrect sequence number(>VT(S)) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO!STAT $Cref STAT_S_N_PS_N_R(TCV_LIST,TCV_N_PS,VR_MR,VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [8] LT_PCO?ER(VR_SQ:=BIT_TO_INT(ER.N_SQ), VT_MS:=BIT_TO_INT(ER.N_MR)) CANCEL T_Wait $Cref ER_R_GEN(VR_SQ) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* VT(PA)<=STAT.N(PS)<=VT(PS), VT(A)<=STAT.N(R)<=VT(S), list element<=VT(S) */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P33 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a STAT PDU that poll sequence number and SD PDU sequence number are correct but its list elements are not increasing order. */ $DefaultsRef $Comment /* Ref. 5.0 i, Fig. 20(44, 45 and 41 of 51)/PICS PC5.1 */ $SelectExprId State10_S_P $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a STAT PDU that poll sequence number and SD PDU sequence number are correct but its list elements are not increasing order. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [6] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB3 $Line [9] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB4 $Line [12] LT_PCO?POLL(TCV_N_PS:=BIT_TO_INT(POLL.N_PS)) CANCEL T_Opr $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] (TCV_LIST:=APPEND_LIST(TCV_LIST,VR_R-1), TCV_LIST:=APPEND_LIST(TCV_LIST,VR_R-2)) $Cref $VerdictId $Comment /* list elements are not increasing order */ $End_BehaviourLine $BehaviourLine $LabelId $Line [14] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [15] LT_PCO!STAT $Cref STAT_S_N_PS_N_R(TCV_LIST,TCV_N_PS,VR_MR,VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [16] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB5 $Line [17] LT_PCO?ER(VR_SQ:=BIT_TO_INT(ER.N_SQ), VT_MS:=BIT_TO_INT(ER.N_MR)) CANCEL T_Wait $Cref ER_R_GEN(VR_SQ) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [18] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [19] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [17] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [18] GOTO LB5 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [17] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [18] GOTO LB5 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [17] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [18] GOTO LB5 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [17] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] +TS_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +TS_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +TS_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* VT(PA)<=STAT.N(PS)<=VT(PS), VT(A)<=STAT.N(R)<=VT(S), list element n >= list element n+1 */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P38_1 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a USTAT PDU that list element has incorrect sequence number. */ $DefaultsRef $Comment /* Ref. 5.0 i, Fig. 20(43 of 51)/PICS PC5.1 */ $SelectExprId State10_SD $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a USTAT PDU that list element has incorrect sequence number. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [6] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB3 $Line [9] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] LT_PCO!USTAT $Cref USTAT_S_LIST(VR_R+1,VR_R+2,VR_MR,VR_R-1) $VerdictId $Comment /* list element has incorrect sequence number */ $End_BehaviourLine $BehaviourLine $LabelId $Line [12] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB4 $Line [13] LT_PCO?ER(VR_SQ:=BIT_TO_INT(ER.N_SQ), VT_MS:=BIT_TO_INT(ER.N_MR)) CANCEL T_Wait $Cref ER_R_GEN(VR_SQ) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [14] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [15] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +TS_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +TS_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* VT(PA)<=STAT.N(PS)<=VT(PS), VT(A)<=STAT.N(R)<=VT(S), list element n >= list element n+1 */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P38_2 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a USTAT PDU that list elements are not increasing order. */ $DefaultsRef $Comment /* Ref. 5.0 i, Fig. 20(43 of 51)/PICS PC5.1 */ $SelectExprId State10_SD $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a USTAT PDU that list elements are not increasing order. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [6] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB3 $Line [9] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] LT_PCO!USTAT $Cref USTAT_S_LIST(VR_R-1,VR_R-2,VR_MR,VR_R-1) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB4 $Line [13] LT_PCO?ER(VR_SQ:=BIT_TO_INT(ER.N_SQ), VT_MS:=BIT_TO_INT(ER.N_MR)) CANCEL T_Wait $Cref ER_R_GEN(VR_SQ) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [14] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [15] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +TS_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +TS_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* VT(PA)<=STAT.N(PS)<=VT(PS), VT(A)<=STAT.N(R)<=VT(S), list element n >= list element n+1 */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P39 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a USTAT PDU that SD PDU sequence number is incorrect. */ $DefaultsRef $Comment /* Ref. 5.0 i, Fig. 20(43 of 51)/PICS PC5.1 */ $SelectExprId State10_SD $Description /* Verify that the IUT, at state 10, sends a ER PDU and goes to state 7 on reception of a USTAT PDU that list elements are not increasing order. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [6] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB3 $Line [9] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] LT_PCO!USTAT $Cref USTAT_S_LIST(VR_R-1,VR_R,VR_MR,VR_R+1) $VerdictId $Comment /* USTAT.N(R) > VT(S) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [12] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB4 $Line [13] LT_PCO?ER(VR_SQ:=BIT_TO_INT(ER.N_SQ), VT_MS:=BIT_TO_INT(ER.N_MR)) CANCEL T_Wait $Cref ER_R_GEN(VR_SQ) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [14] +S7_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [15] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] GOTO LB4 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +TS_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +TS_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Opr $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* USTAT.N(R) > VT(S) */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P40 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT accepts a UD PDU at state 10. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.2 */ $SelectExprId $Description /* Verify that the IUT accpets a UD PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_V_P41 $TestGroupRef af_test_0067_001/PC/STATE_10/VAL/ $TestPurpose /* Verify that the IUT accepts a MD PDU at state 10. */ $DefaultsRef $Comment /* Ref 5.0 h, Fig. 20(47 of 51)/PICS PC5.3 */ $SelectExprId $Description /* Verify that the IUT accpets a MD PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INV $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S10_IV_I1 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is not 32-bit aligned at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I2 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is not 32-bit aligned at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGAK $Cref BGAK_S_INV(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I3 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is not 32-bit aligned at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I4 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is not 32-bit aligned at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDPDU $Cref END_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I6 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is not 32-bit aligned at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!RS $Cref RS_S_INV(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I10 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is not 32-bit aligned at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_INV(VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I14 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is not 32-bit aligned at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!UD $Cref UD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I15 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is not 32-bit aligned at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!MD $Cref MD_S_INV $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I16 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 8, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGN PDU which is 32-bit aligned but is not the proper length of the BGN PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VT_SQ:=INC_MOD_8(VT_SQ,1),VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGN $Cref IVBGN_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I17 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 9, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGAK PDU which is 32-bit aligned but is not the proper length of the BGAK PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!IVBGAK $Cref IVBGAK_S_INV(TCV_OCT,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [5] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I18 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 10, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid BGREJ PDU which is 32-bit aligned but is not the proper length of the BGREJ PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVBGREJ $Cref IVBGREJ_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I19 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 11, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid END PDU which is 32-bit aligned but is not the proper length of the END PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVEND $Cref IVEND_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I20_1 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is 32-bit aligned but is not the proper length of the ENDAK PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('00000000'O) $VerdictId $Comment /* extra 4 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I20_2 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 12, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ENDAK PDU which is not 32-bit aligned and is not the proper length of the ENDAK PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVENDAK $Cref IVENDAK_S_INV('0000'O) $VerdictId $Comment /* extra 2 octets in ENDAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I21 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 13, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RS PDU which is 32-bit aligned but is not the proper length of the RS PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(UU_Max_Len + ((4 - (UU_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (UU_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVRS $Cref IVRS_S_INV(TCV_OCT,VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I22_1 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is 32-bit aligned but is not the proper length of the RSAK PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I22_2 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 14, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid RSAK PDU which is not 32-bit aligned and is not the proper length of the RSAK PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVRSAK $Cref IVRSAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in RSAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I23_1 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is 32-bit aligned but is not the proper length of the ER PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('00000000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 4 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I23_2 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 15, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ER PDU which is not 32-bit aligned and is not the proper length of the ER PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVER $Cref IVER_S_INV('0000'O,VT_SQ,VR_MR) $VerdictId $Comment /* extra 2 octets in ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I24_1 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is 32-bit aligned but is not the proper length of the ERAK PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('00000000'O,VR_MR) $VerdictId $Comment /* extra 4 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I24_2 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 16, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid ERAK PDU which is not 32-bit aligned and is not the proper length of the ERAK PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVERAK $Cref IVERAK_S_INV('0000'O,VR_MR) $VerdictId $Comment /* extra 2 octets in ERAK PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I25 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 3, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid SD PDU which is 32-bit aligned but is not the proper length of the SD PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSD $Cref IVSD_S_INV(TCV_OCT,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I26_1 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is 32-bit aligned but is not the proper length of the POLL PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('00000000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 4 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I26_2 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 4, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid POLL PDU which is not 32-bit aligned and is not the proper length of the POLL PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVPOLL $Cref IVPOLL_S_INV('0000'O,VT_PS,VT_S) $VerdictId $Comment /* extra 2 octets in POLL PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I27_1 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is 32-bit aligned but is not the proper length of the STAT PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'00000000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I27_2 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 5, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid STAT PDU which is not 32-bit aligned and is not the proper length of the STAT PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVSTAT $Cref IVSTAT_S_INV(TCV_OCT,'0000'O,VT_PS,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in STAT PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I28_1 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is 32-bit aligned but is not the proper length of the USTAT PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'00000000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 4 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I28_2 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTST PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 6, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid USTAT PDU which is not 32-bit aligned and is not the proper length of the USTAT PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!IVUSTAT $Cref IVUSTAT_S_INV(VR_R,VR_R+1,'0000'O,VR_MR,VR_R) $VerdictId $Comment /* extra 2 octets in USTAT PDU. list elements have no meaning */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I29 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid UD PDU which is 32-bit aligned but is not the proper length of the UD PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVUD $Cref IVUD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I30 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 7, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid MD PDU which is 32-bit aligned but is not the proper length of the MD PDU at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (TCV_OCT:=INT_TO_HEX(0,(Info_Max_Len + ((4 - (Info_Max_Len MOD 4)) MOD 4) + 4)*2)) $Cref $VerdictId $Comment /* length = (Info_Max_Len + PAD + 4) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!IVMD $Cref IVMD_S_INV(TCV_OCT) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IV_I31 $TestGroupRef af_test_0067_001/PC/STATE_10/INV/ $TestPurpose /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 10. */ $DefaultsRef $Comment /* Ref. 7.1, Fig. 20(47 of 51)/PICS PD3 */ $SelectExprId $Description /* Verify that the IUT ignores an invalid PDU which has an unknown PDU type code at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO!BGN $Cref BGN_S_CODE(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId INOP $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S10_IO_P4 $TestGroupRef af_test_0067_001/PC/STATE_10/INOP/ $TestPurpose /* Verify that the IUT, at state 10, goes to state 1 on reception of BGREJ PDU. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(36 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 1 on reception of BGREJ PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGREJ $Cref BGREJ_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IO_P6 $TestGroupRef af_test_0067_001/PC/STATE_10/INOP/ $TestPurpose /* Verify that the IUT, at state 10, goes to state 1 on reception of ENDAK PDU. */ $DefaultsRef $Comment /* Ref. 5.0 g, Fig. 20(36 of 51)/PICS PC8 */ $SelectExprId $Description /* Verify that the IUT, at state 10, goes to state 1 on reception of ENDAK PDU. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ENDAK $Cref ENDAK_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $End_TestGroup $End_TestGroup $TestGroup $TestGroupId SP $SelectExprId $Objective /* System Parameters */ $TestGroup $TestGroupId TIMER_TESTS $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId S2_CC_T1 $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestPurpose /* Verify that the IUT, at state 2, sends a END PDU and goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $DefaultsRef $Comment /* Ref. 5.0 g, 7.6 d, Fig. 20(9 of 51)/PICS SP1 */ $SelectExprId $Description /* Verify that the IUT, at state 2, sends a END PDU and goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S2_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (count:=1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [5] LT_PCO?BGN $Cref BGN_R_RET(VR_SQ,VT_MS) $VerdictId $Comment /* identical to the last BGN PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] CANCEL T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] (count:=count+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] [count < Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] [count >=Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB3 $Line [12] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [13] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S4_CC_T1 $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestPurpose /* Verify that the IUT, at state 4, goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $DefaultsRef $Comment /* Ref. 5.0 g, 7.6 d, Fig. 20(15 of 51)/PICS SP1 */ $SelectExprId $Description /* Verify that the IUT, at state 4, goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S4_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (count:=1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [5] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $Comment /* identical to the last END PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] CANCEL T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] (count:=count+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] [count < Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] [count >=Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] ?TIMEOUT T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S5_CC_T1 $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestPurpose /* Verify that the IUT, at state 5, sends a END PDU and goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $DefaultsRef $Comment /* Ref. 5.0 g, 7.6 d, Fig. 20(18 of 51)/PICS SP1 */ $SelectExprId $Description /* Verify that the IUT, at state 5, sends a END PDU and goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S5_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (count:=1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [5] LT_PCO?RS $Cref RS_R_RET(VR_SQ,VT_MS) $VerdictId $Comment /* identical to the last RS PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] CANCEL T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] (count:=count+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] [count < Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] [count >=Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB3 $Line [12] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [13] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S7_CC_T1 $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestPurpose /* Verify that the IUT, at state 7, sends a END PDU and goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $DefaultsRef $Comment /* Ref. 5.0 g, 7.6 d, Fig. 20(24 of 51)/PICS SP1 */ $SelectExprId $Description /* Verify that the IUT, at state 7, sends a END PDU and goes to state 1 when the Timer Timer_CC is expired and the value of the connection control state variable exceeds the maximum value. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S7_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (count:=1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [2] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [5] LT_PCO?ER $Cref ER_R_RET(VR_SQ,VT_MS) $VerdictId $Comment /* identical to the last ER PDU */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] CANCEL T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] (count:=count+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] [count < Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] [count >=Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB3 $Line [12] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [13] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [14] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [13] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_POLL_T3 $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestPurpose /* Verify that the IUT, at state 10, sends a POLL PDU when the Timer Timer_POLL is expired . */ $DefaultsRef $Comment /* Ref. 7.6 a, Fig. 20(37 of 51)/PICS SP5 */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a POLL PDU when the Timer Timer_POLL is expired. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] START Timer_POLL $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] ?TIMEOUT Timer_POLL $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?POLL CANCEL T_Wait $Cref POLL_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_KEEP_ALIVE_T4 $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestPurpose /* Verify that the IUT, at state 10, sends a POLL PDU when the Timer Timer_KEEP_ALIVE is expired . */ $DefaultsRef $Comment /* Ref. 7.6 b, Fig. 20(37 of 51)/PICS SP6 */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a POLL PDU when the Timer Timer_KEEP_ALIVE is expired. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] START Timer_POLL $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] ?TIMEOUT Timer_POLL $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] CANCEL T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] START Timer_KEEP_ALIVE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] ?TIMEOUT Timer_KEEP_ALIVE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [9] LT_PCO?POLL CANCEL T_Wait $Cref POLL_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [10] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_IDLE_T5 $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestPurpose /* Verify that the IUT, at state 10, sends a POLL PDU when the Timer Timer_IDLE is expired . */ $DefaultsRef $Comment /* Ref. 7.6 c, Fig. 20(37 of 51)/PICS SP8 */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a POLL PDU when the Timer Timer_IDLE is expired. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] START Timer_POLL $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] ?TIMEOUT Timer_POLL $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?POLL(TCV_N_PS:= BIT_TO_INT( POLL.N_PS)) $Cref POLL_R_GEN $VerdictId $Comment /* IUT start Timer_KEEP_ALIVE */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] CANCEL T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO!STAT $Cref STAT_S_N_PS_N_R(TCV_LIST,TCV_N_PS,VR_MR,VR_R) $VerdictId $Comment /* IUT start Timer_IDLE */ $End_BehaviourLine $BehaviourLine $LabelId $Line [7] START Timer_IDLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] ?TIMEOUT Timer_IDLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [10] LT_PCO?POLL CANCEL T_Wait $Cref POLL_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [11] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [12] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [11] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [10] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $Begin_TestCase $TestCaseId S10_NO_RESPONSE_T6 $TestGroupRef af_test_0067_001/SP/TIMER_TESTS/ $TestPurpose /* Verify that the IUT, at state 10, sends a END PDU when the Timer Timer_NO_RESPONSE is expired . */ $DefaultsRef $Comment /* Ref. 7.6 a, Fig. 20(37 of 51)/PICS SP7 */ $SelectExprId $Description /* Verify that the IUT, at state 10, sends a END PDU when the Timer Timer_NO_RESPONSE is expired. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $Comment /* IUT start Timer_NO_RESPONSE */ $End_BehaviourLine $BehaviourLine $LabelId $Line [1] START Timer_NO_RESPONSE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] ?TIMEOUT Timer_NO_RESPONSE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [4] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +S1_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestCase $End_TestGroup $TestGroup $TestGroupId PARAM $SelectExprId $Objective /* */ $Begin_TestCase $TestCaseId SP3_MaxPD $TestGroupRef af_test_0067_001/SP/PARAM/ $TestPurpose /* Check the value of MaxPD system parameter(Maximum number of SD PDUs before transmission of a POLL PDU). */ $DefaultsRef $Comment /* Ref. 7.7 c/PICS SP2 */ $SelectExprId $Description /* Check the value of MaxPD system parameter(Maximum number of SD PDUs before transmission of a POLL PDU). */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (count:=0) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [2] $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [4] LT_PCO?SD(VR_R:=INC_MOD_24(VR_R,1)) CANCEL T_Opr $Cref SD_R_GEN(VR_R) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] (count:=count+1) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] [count>=Max_PD] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +S10_VERIFY $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [9] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] [count= Max_CC] $Cref $VerdictId I $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?OTHERWISE $Cref $VerdictId I $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO?OTHERWISE $Cref $VerdictId I $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $TestStepGroup $TestStepGroupId PREAMBLE $Begin_TestStep $TestStepId S1_PREAMBLE $TestStepRef af_test_0067_001/PREAMBLE/ $Objective /* Procedure used to place the IUT at state 1(IDLE) from any state. */ $DefaultsRef $Description /* Procedure used to place the IUT at state 1 from any state. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] LT_PCO!BGREJ $Cref BGREJ_S_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [2] ?TIMEOUT T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] (count:=0) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [4] LT_PCO!ENDPDU(count:=count+1) $Cref END_S_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB3 $Line [6] LT_PCO?ENDAK CANCEL Timer_CC $Cref ENDAK_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB3 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] [count < Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] [count >= Max_CC] $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] LT_PCO?OTHERWISE $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] LT_PCO?OTHERWISE $Cref $VerdictId (I) $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S2_PREAMBLE $TestStepRef af_test_0067_001/PREAMBLE/ $Objective /* Procedure used to place the IUT at state 2(OUTGOING CONNECTION PENDING) from any state. */ $DefaultsRef $Description /* Procedure used to place the IUT at state 2 from any state. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref BGN_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?BGN(VR_SQ:=BIT_TO_INT(BGN.N_SQ), VT_MS:=BIT_TO_INT(BGN.N_MR)) CANCEL T_Opr $Cref BGN_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] ?TIMEOUT T_Opr $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S4_PREAMBLE $TestStepRef af_test_0067_001/PREAMBLE/ $Objective /* Procedure used to place the IUT at state 4(OUTGOING DISCONNECTION PENDING) from any state. */ $DefaultsRef $Description /* Procedure used to place the IUT at state 4 from any state. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDPDU CANCEL T_Opr $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] ?TIMEOUT T_Opr $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S5_PREAMBLE $TestStepRef af_test_0067_001/PREAMBLE/ $Objective /* Procedure used to place the IUT at state 5(OUTGOING RESYNCHRONIZATION PENDING) from any state. */ $DefaultsRef $Description /* Procedure used to place the IUT at state 5 from any state. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] $Cref RS_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Opr $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ), VT_MS:=BIT_TO_INT(RS.N_MR)) CANCEL T_Opr $Cref RS_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] ?TIMEOUT T_Opr $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?OTHERWISE $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S7_PREAMBLE $TestStepRef af_test_0067_001/PREAMBLE/ $Objective /* Procedure used to place the IUT at state 7(OUTGOING RECOVERY PENDING) from any state. */ $DefaultsRef $Description /* Procedure used to place the IUT at state 7 from any state. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S10_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $Comment /* VT_S=0 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VT_S:=INC_MOD_24(VT_S,3)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO!SD $Cref SD_S_GEN(VT_S) $VerdictId $Comment /* VT_S=3 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [4] (VT_S:=INC_MOD_24(VT_S,1),VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO!POLL $Cref POLL_S_N_S(VT_PS,VT_S-3) $VerdictId $Comment /* VR(H)>POLL.N(S) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [6] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [7] LT_PCO?ER(VR_SQ:=BIT_TO_INT(ER.N_SQ), VT_MS:=BIT_TO_INT(ER.N_MR)) CANCEL T_Wait $Cref ER_R_GEN(VR_SQ) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?USTAT $Cref USTAT_R_LIST(1, 3,1) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [8] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] ?TIMEOUT T_Wait $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] LT_PCO?OTHERWISE $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [8] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S10_PREAMBLE $TestStepRef af_test_0067_001/PREAMBLE/ $Objective /* Procedure used to place the IUT at state 10(DATA TRANSFER READY) from any state. */ $DefaultsRef $Description /* Procedure used to place the IUT at state 10 from any state. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] +S1_PREAMBLE $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] (count:=0) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO!BGN(count:=count+1) $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [5] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL Timer_CC $Cref BGAK_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +Initialize_State_Variables $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] ?TIMEOUT Timer_CC $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] [count < Max_CC] $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [7] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] [count >= Max_CC] $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [7] +postamble $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?OTHERWISE $Cref $VerdictId (I) $End_BehaviourLine $BehaviourLine $LabelId $Line [6] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $End_TestStepGroup $TestStepGroup $TestStepGroupId VERIFY $Begin_TestStep $TestStepId S1_VERIFY $TestStepRef af_test_0067_001/VERIFY/ $Objective /* Procedure used to verify that the IUT is at state 1. */ $DefaultsRef $Description /* Procedure used to verify that the IUT is at state 1. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGAK $Cref BGAK_S_GEN(VR_MR) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_SSCOP $VerdictId (P) $Comment /* IUT was at state 1 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S2_VERIFY $TestStepRef af_test_0067_001/VERIFY/ $Objective /* Procedure used to verify that the IUT is at state 2. */ $DefaultsRef $Description /* Procedure used to verify that the IUT is at state 2. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* VR(SQ)<>N(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL T_Wait $Cref BGAK_R_GEN $VerdictId (P) $Comment /* IUT was at state 2 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S4_VERIFY $TestStepRef af_test_0067_001/VERIFY/ $Objective /* Procedure used to verify that the IUT is at state 4. */ $DefaultsRef $Description /* Procedure used to verify that the IUT is at state 4. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* VR(SQ)=N(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) $Cref BGAK_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [5] LT_PCO?ENDPDU CANCEL T_Wait $Cref END_R_GEN $VerdictId (P) $Comment /* IUT was at state 4 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?ENDPDU $Cref END_R_USER $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S5_VERIFY $TestStepRef af_test_0067_001/VERIFY/ $Objective /* Procedure used to verify that the IUT is at state 5. */ $DefaultsRef $Description /* Procedure used to verify that the IUT is at state 5. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] (VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!BGN $Cref BGN_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* VR(SQ)=N(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?BGAK(VT_MS:=BIT_TO_INT(BGAK.N_MR)) CANCEL T_Wait $Cref BGAK_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB2 $Line [5] LT_PCO?RS(VR_SQ:=BIT_TO_INT(RS.N_SQ), VT_MS:=BIT_TO_INT(RS.N_MR)) CANCEL T_Wait $Cref RS_R_RET(VR_SQ, VT_MS) $VerdictId (P) $Comment /* IUT was at state 5 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [6] GOTO LB2 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [5] +TS_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S7_VERIFY $TestStepRef af_test_0067_001/VERIFY/ $Objective /* Procedure used to verify that the IUT is at state 7. */ $DefaultsRef $Description /* Procedure used to verify that the IUT is at state 7. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] (VT_SQ:=INC_MOD_8(VT_SQ,1), VR_MR:=GET_VR_MR()) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!ER $Cref ER_S_GEN(VT_SQ,VR_MR) $VerdictId $Comment /* VR(SQ)<>N(SQ) */ $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?ERAK(VT_MS:=BIT_TO_INT(ERAK.N_MR)) CANCEL T_Wait $Cref ERAK_R_GEN $VerdictId (P) $Comment /* IUT was at state 7 */ $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?UD $Cref UD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?MD $Cref MD_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] +TS_Wait $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $Begin_TestStep $TestStepId S10_VERIFY $TestStepRef af_test_0067_001/VERIFY/ $Objective /* Procedure used to verify that the IUT is at state 10. */ $DefaultsRef $Description /* Procedure used to verify that the IUT is at state 10. */ $BehaviourDescription $BehaviourLine $LabelId $Line [0] (VT_PS:=INC_MOD_24(VT_PS,1)) $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [1] LT_PCO!POLL $Cref POLL_S_GEN(VT_PS,VT_S) $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [2] START T_Wait $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId LB1 $Line [3] LT_PCO?STAT(VT_MS:=BIT_TO_INT(STAT.N_MR)) CANCEL T_Wait $Cref STAT_R_N_R_S10_Verify(VT_PS) $VerdictId (P) $End_BehaviourLine $BehaviourLine $LabelId $Line [3] LT_PCO?POLL $Cref POLL_R_GEN $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [4] GOTO LB1 $Cref $VerdictId $End_BehaviourLine $BehaviourLine $LabelId $Line [3] ?TIMEOUT T_Wait $Cref $VerdictId (F) $End_BehaviourLine $BehaviourLine $LabelId $Line [4] +postamble $Cref $VerdictId $End_BehaviourLine $End_BehaviourDescription $Comment /* */ $End_TestStep $End_TestStepGroup $End_TestStepLibrary $End_DynamicPart $End_Suite